Hello everyone.
I get E350M1 motherboard and want to report some things i tested.
This can be especially interesting to Paul Menzel and some others, who i see adding patches related to this motherboard few last months.
Most information is available on http://www.coreboot.org/ASRock_E350M1 so i post only difference with my experience.
Wiki update: PS/2 Keyboard - NOT working - with init_ps2_keyboard option it blinks during post but still not working in OS PS/2 Mouse - NOT working
Regressions: Ethernet - NOT working POST time 5-10 secounds instead of 1-3
I cannot surely say after which commit regressions occur. I was using gcb891de as latest and ec6f043 as old surely working (most close to latest progressive changes on wiki page).
Also want to add i was unable to get valid vgabios.bin using instructions at http://www.coreboot.org/VGA_support, nor by ./bios_extract nor by script from Peter Stuge. So removed link to vgabios on wiki page allowed me to successfully build.
Thanks, all!
Dear openvoid,
Am Sonntag, den 14.04.2013, 22:09 +0400 schrieb openvoid:
[…]
Also want to add i was unable to get valid vgabios.bin using instructions at http://www.coreboot.org/VGA_support, nor by ./bios_extract nor by script from Peter Stuge. So removed link to vgabios on wiki page allowed me to successfully build.
So you currently do not use any VGA BIOS? Could you post (even paste) the exact steps you tried please.
Thanks,
Paul
Hello Paul, All.
So you currently do not use any VGA BIOS? Could you post (even paste) the exact steps you tried please.
currently i use Alien's vga bios file 65536 bytes from end of page http://www.coreboot.org/index.php?title=ASRock_E350M1&oldid=11114
before i was trying to use instructions from http://www.coreboot.org/VGA_support to get bios from vendor BIOS bios_extract on (flashrom -r bios.rom) file - failed (Error: Unable to detect BIOS Image type.) script from Peter Stuge on working linux - gave me 57856 bytes file using which i get no video (and seems not even POST complete)
not sure if the size matters to success, but truncating Alien's file from 65536 to 57856 and try to diff with mine shows they are different though looking very simillar in the beginning and in the end in HEX.
With best wishes, openvoid
Dear openvoid,
welcome to coreboot and thank you for your report!
Am Sonntag, den 14.04.2013, 22:09 +0400 schrieb openvoid:
I get E350M1 motherboard
In #coreboot on <irc.freenode.net> openvoid confirmed that this is the ASRock E350M1 and not the ASRock E350M1/USB3.
and want to report some things i tested.
Thanks. I assume you also opened the ticket 192 in coreboot’s Trac instance [1]. Thanks for this, but we should try to keep discussing this on this list (one thread for each problem) as the Trac tracker is not used that much anymore.
What payload do you use?
This can be especially interesting to Paul Menzel and some others, who i see adding patches related to this motherboard few last months.
Yes, thanks a lot!
Most information is available on http://www.coreboot.org/ASRock_E350M1 so i post only difference with my experience.
[…]
I cannot surely say after which commit regressions occur. I was using gcb891de as latest
The g at the very beginning stands for git, so here is the revision you reference.
$ git show cb891de commit cb891de07ffe605897010776fc1becc9589d3648 Author: Paul Menzel paulepanter@users.sourceforge.net Date: Sat Apr 13 18:35:32 2013 +0200
cbmem: parse_cbtable: Use length modifier `ll` `u64` argument
Reviewed-on: http://review.coreboot.org/3084
and ec6f043 as old surely working (most close to latest progressive changes on wiki page).
$ git show ec6f043 commit ec6f043c253355483bd065c39adc91bad2647ee9 Author: Denis 'GNUtoo' Carikli GNUtoo@no-log.org Date: Thu Jun 14 14:19:09 2012 +0200
llshell: fix build without romcc
Reviewed-on: http://review.coreboot.org/1101
I have reordered your message, so I can comment on the problems now.
Wiki update: PS/2 Keyboard - NOT working - with init_ps2_keyboard option it blinks during post but still not working in OS PS/2 Mouse - NOT working
I have different experience. Once it did not work at all. The other time it worked somewhat but pressing one key it appeared several times on the screen as reported to the list [2][3].
Regressions: Ethernet - NOT working
Thanks for finding the responsible in [1] using bisection!
POST time 5-10 seconds instead of 1-3
Same here. Please see my message to the mailing list [4]
Thanks,
Paul
[1] https://tracker.coreboot.org/trac/coreboot/ticket/192 [2] http://www.coreboot.org/pipermail/coreboot/2013-March/075584.html [3] http://www.coreboot.org/pipermail/coreboot/2013-April/075586.html [4] http://www.coreboot.org/pipermail/coreboot/2013-April/075602.html
Hello all.
I have different experience. Once it did not work at all. The other time it worked somewhat
I did more accurate testing.
menuconfig: default +ASRock +E350M1 +Use VGA BIOS payload: SeaBIOS system: Windows 8 and Trisquel 6.0 dual-boot with GRUB2 snapshot: cb891de
Native PS/2 keyboard BTC 5211 GRUB: Works as fine as possible to test in GRUB Win8: Not working Trisquel6: Not working (during POST leds blink, even CONFIG_DRIVERS_PS2_KEYBOARD is not set)
Native PS/2 mouse Logitech M-SBF90 GRUB: N/A Win8: Not working Trisquel6: Not working
Dual USB-PS/2 capable mouse Logitech M-BT58 with PS/2 adaptor GRUB: N/A Win8: Not working Trisquel6: Works fine
Hope my information will help make coreboot better. Or may be just usable to update wiki :)
Cheers!
Hello all.
I did some tests of how suspend works.
menuconfig: default +ASRock +E350M1 +Use VGA BIOS payload: SeaBIOS system: Windows 8 and Trisquel 6.0 dual-boot with GRUB2 snapshot: cb891de
At first there is mess with common terms used for low power modes do describe it correct. I'd prefer to use OS neutral terms for it but only source i have is [1] which do not provide much. I see there Sleep=Suspend for mode, when power is lowered to wake up fast but necessary to do it successfull; Hibernate for dumping memory to disk and complete power off; and some Hybrid mode looks like mix of both.
In short, my tests say with Win8 suspend works and with Trisquel6 not. Below are more details.
Win8: Sleep button is available, but pressing it seems actually activate Hybrid mode. Computer looks completely powered off (with vendor BIOS power led was blinking). By pressing power button computer resumes from POST but power to USB devices is not restored (mouse do not lit). So computer wakes up with no keyboard working and in GRUB i cannot select to boot Win8. (If leave GRUB to boot Trisquel nor mouse nor keyboard are working.) If to unplug power during low power mode (or power off by holding power button 4 secounds before it boots and power on again) USB power is restored. I can select to boot Win8. System wakes up in same state it was left.
Trisquel6. Suspend button is available. I am not sure what low power mode is activated by pressing but computer looks completely powered off. With pressing power button same issue with USB devices in GRUB, but during boot they got reinitialised (as system boots fresh) and work ok. AFAIK when resume with linux happen GRUB sees it and do not show OS menu but doing resume. So may be issue with resume not working in linux is with BIOS-GRUB communication.
Hope my information can somehow help.
Cheers!
Dave's isolated the issue and is testing the patch. This should be pushed today or tomorrow.
Martin
On 04/16/2013 09:04 AM, Paul Menzel wrote:
Dear openvoid,
welcome to coreboot and thank you for your report!
Am Sonntag, den 14.04.2013, 22:09 +0400 schrieb openvoid:
I get E350M1 motherboard
In #coreboot on <irc.freenode.net> openvoid confirmed that this is the ASRock E350M1 and not the ASRock E350M1/USB3.
and want to report some things i tested.
Thanks. I assume you also opened the ticket 192 in coreboot’s Trac instance [1]. Thanks for this, but we should try to keep discussing this on this list (one thread for each problem) as the Trac tracker is not used that much anymore.
What payload do you use?
This can be especially interesting to Paul Menzel and some others, who i see adding patches related to this motherboard few last months.
Yes, thanks a lot!
Most information is available on http://www.coreboot.org/ASRock_E350M1 so i post only difference with my experience.
[…]
I cannot surely say after which commit regressions occur. I was using gcb891de as latest
The g at the very beginning stands for git, so here is the revision you reference.
$ git show cb891de commit cb891de07ffe605897010776fc1becc9589d3648 Author: Paul Menzel <paulepanter@users.sourceforge.net> Date: Sat Apr 13 18:35:32 2013 +0200 cbmem: parse_cbtable: Use length modifier `ll` `u64` argument Reviewed-on: http://review.coreboot.org/3084
and ec6f043 as old surely working (most close to latest progressive changes on wiki page).
$ git show ec6f043 commit ec6f043c253355483bd065c39adc91bad2647ee9 Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Date: Thu Jun 14 14:19:09 2012 +0200 llshell: fix build without romcc Reviewed-on: http://review.coreboot.org/1101
I have reordered your message, so I can comment on the problems now.
Wiki update: PS/2 Keyboard - NOT working - with init_ps2_keyboard option it blinks during post but still not working in OS PS/2 Mouse - NOT working
I have different experience. Once it did not work at all. The other time it worked somewhat but pressing one key it appeared several times on the screen as reported to the list [2][3].
Regressions: Ethernet - NOT working
Thanks for finding the responsible in [1] using bisection!
POST time 5-10 seconds instead of 1-3
Same here. Please see my message to the mailing list [4]
Thanks,
Paul
[1] https://tracker.coreboot.org/trac/coreboot/ticket/192 [2] http://www.coreboot.org/pipermail/coreboot/2013-March/075584.html [3] http://www.coreboot.org/pipermail/coreboot/2013-April/075586.html [4] http://www.coreboot.org/pipermail/coreboot/2013-April/075602.html
Paul (and/or anybody else that can test this patch on a E350M1),
Commit 23023a5 correctly enabled the SB800 GPP PCIe ports but didn't distribute the PCIe lanes for the GPP_CFGMODEs other than GPP_CFGMODE_X4000.
The hardware I originally tested this on only used GPP port A, so it didn't really matter if it was x1/x2/x4. The E350M1 board is evidently using two x1 channels to two PCIe devices so it needs the lanes distributed correctly.
I wanted to know if anybody could test this on a E350M1 to see if it fixes the problem.
Any takers?
Thanks, Dave
From ee0af1d0478ddbe67562fe7e967fb419f85a3ade Mon Sep 17 00:00:00 2001
From: Dave Frodin dave.frodin@se-eng.com Date: Wed, 17 Apr 2013 08:51:49 -0600 Subject: [PATCH] AMD/SB800: Define the GPP PCIe lane distribution
A bug was created with commit 23023a5 which correctly enabled the GPP PCIe ports, but didn't distribute the 4 PCIe lanes to those ports.
Change-Id: I1dc7eaa59ad0a49be0e6e59f5ee40c4c121a5110 Signed-off-by: Dave Frodin dave.frodin@se-eng.com --- src/southbridge/amd/cimx/sb800/late.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index cfdf9f2..74b2d08 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -368,13 +368,13 @@ static void sb800_enable(device_t dev) /* the first sb800 device */ switch (GPP_CFGMODE) { /* config the GPP PCIe ports */ case GPP_CFGMODE_X2200: - abcfg_reg(0xc0, 0x01FF, 0x030); /* x2 Port_0, x2 Port_1 */ + abcfg_reg(0xc0, 0x01FF, 0x032); /* x2 Port_0, x2 Port_1 */ break; case GPP_CFGMODE_X2110: - abcfg_reg(0xc0, 0x01FF, 0x070); /* x2 Port_0, x1 Port_1&2 */ + abcfg_reg(0xc0, 0x01FF, 0x073); /* x2 Port_0, x1 Port_1&2 */ break; case GPP_CFGMODE_X1111: - abcfg_reg(0xc0, 0x01FF, 0x0F0); /* x1 Port_0&1&2&3 */ + abcfg_reg(0xc0, 0x01FF, 0x0F4); /* x1 Port_0&1&2&3 */ break; case GPP_CFGMODE_X4000: default: -- 1.7.9
----- Original Message -----
From: "Paul Menzel" paulepanter@users.sourceforge.net To: "openvoid" openvoid@abandoned.su Cc: coreboot@coreboot.org Sent: Tuesday, April 16, 2013 9:04:22 AM Subject: Re: [coreboot] AsRock E350M1 report: Ethernet adapter not initialized
Dear openvoid,
welcome to coreboot and thank you for your report!
Am Sonntag, den 14.04.2013, 22:09 +0400 schrieb openvoid:
I get E350M1 motherboard
In #coreboot on <irc.freenode.net> openvoid confirmed that this is the ASRock E350M1 and not the ASRock E350M1/USB3.
and want to report some things i tested.
Thanks. I assume you also opened the ticket 192 in coreboot’s Trac instance [1]. Thanks for this, but we should try to keep discussing this on this list (one thread for each problem) as the Trac tracker is not used that much anymore.
What payload do you use?
This can be especially interesting to Paul Menzel and some others, who i see adding patches related to this motherboard few last months.
Yes, thanks a lot!
Most information is available on http://www.coreboot.org/ASRock_E350M1 so i post only difference with my experience.
[…]
I cannot surely say after which commit regressions occur. I was using gcb891de as latest
The g at the very beginning stands for git, so here is the revision you reference.
$ git show cb891de commit cb891de07ffe605897010776fc1becc9589d3648 Author: Paul Menzel <paulepanter@users.sourceforge.net> Date: Sat Apr 13 18:35:32 2013 +0200 cbmem: parse_cbtable: Use length modifier `ll` `u64` argument Reviewed-on: http://review.coreboot.org/3084
and ec6f043 as old surely working (most close to latest progressive changes on wiki page).
$ git show ec6f043 commit ec6f043c253355483bd065c39adc91bad2647ee9 Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Date: Thu Jun 14 14:19:09 2012 +0200 llshell: fix build without romcc Reviewed-on: http://review.coreboot.org/1101
I have reordered your message, so I can comment on the problems now.
Wiki update: PS/2 Keyboard - NOT working - with init_ps2_keyboard option it blinks during post but still not working in OS PS/2 Mouse - NOT working
I have different experience. Once it did not work at all. The other time it worked somewhat but pressing one key it appeared several times on the screen as reported to the list [2][3].
Regressions: Ethernet - NOT working
Thanks for finding the responsible in [1] using bisection!
POST time 5-10 seconds instead of 1-3
Same here. Please see my message to the mailing list [4]
Thanks,
Paul
[1] https://tracker.coreboot.org/trac/coreboot/ticket/192 [2] http://www.coreboot.org/pipermail/coreboot/2013-March/075584.html [3] http://www.coreboot.org/pipermail/coreboot/2013-April/075586.html [4] http://www.coreboot.org/pipermail/coreboot/2013-April/075602.html
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Hello Dave, Paul, all.
Great thanks for fast response and some solution.
I wanted to know if anybody could test this on a E350M1 to see if it fixes the problem.
The code was significally rewritten since 23023a5 The person who did rewriting probably inherited the issue. As I can see now part of code doing same is in sb800.c not in late.c ===147=== static void set_sb800_gpp(device_t dev) ===173=== /* 5.2 Enabling GPP Port A/B/C/D */ //abcfg_reg(0xC0, 0xF << 4, 0x1 << 4); abcfg_reg(0xC0, 0xF << 4, dev->enabled ? 0x1 << (4 + port) : 0);
printk(BIOS_DEBUG, "set_sb800_gpp() 3\n"); /* 5.3 Releasing GPP Reset */ abcfg_reg(0xC0, 0x1 << 8, 0x0 << 8);
/* release training */ abcfg_reg(0xC0, 0xF << 12, 0x0 << 12); ===cut===
And that part i think too
===370=== case (0x15 << 3) | 0: set_sb800_gpp(dev); index = 4; break; case (0x15 << 3) | 1: case (0x15 << 3) | 2: case (0x15 << 3) | 3: break; ===cut===
Any takers?
well, i can test applied patch on older snapshots but do not think it will worth it since master code is rewritten. it is better to get solution for current master.
PS. may be there is some my fault that patch is not much useful, i did report i tested git reverse on current master to Paul, but with checking later i found git was not latest master. when i found it i did fresh git clone to be sure and can confirm the issue still happen with rewritten code.
Thanks to all, openvoid
Dave Frodin wrote:
I wanted to know if anybody could test this on a E350M1 to see if it fixes the problem.
Just checking that this isn't really proposed for inclusion but rather a test patch to see if this change solves the problem?
//Peter
Peter, I think we definitely plan on having it go in. Dave just hasn't been able to actually test it to verify that it fixes the problem. If nobody else gets to it, I'm going to try again to test it tonight.
Martin
On 04/17/2013 03:36 PM, Peter Stuge wrote:
Dave Frodin wrote:
I wanted to know if anybody could test this on a E350M1 to see if it fixes the problem.
Just checking that this isn't really proposed for inclusion but rather a test patch to see if this change solves the problem?
//Peter
Martin Roth wrote:
I think we definitely plan on having it go in.
Does this kind of routing configuration really apply universally to all users of the chipset?
//Peter
On 04/17/2013 06:43 PM, Peter Stuge wrote:
Martin Roth wrote:
I think we definitely plan on having it go in.
Does this kind of routing configuration really apply universally to all users of the chipset?
yes.
//Peter
Hello Dave, Paul, all.
Please ignore my previous message.
I get lost in source tree and messed things up. Sorry.
Any takers?
Tested patch. Works for me.
Thanks for rapid solution.
With best wishes, openvoid
Dear coreboot folks,
Dave pushed this change to Gerrit for review [1]. (Dave, thanks!)
Thanks,
Paul