Patch set updated for coreboot: 15fa0ed Intel Sandybridge: add reserved memory as resources
Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1372
-gerrit
commit 15fa0edd877b491a807340d018369f303aee0722 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Thu Jul 26 23:51:20 2012 +0300
Intel Sandybridge: add reserved memory as resources
Reserved memory resources will get removed from memory table at the end of write_coreboot_table(),
Change-Id: I02711b4be4f25054bd3361295d8d4dc996b2eb3e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/cpu/x86/mtrr/mtrr.c | 4 +++ src/include/device/device.h | 12 ++++++++- src/include/device/resource.h | 1 + src/northbridge/intel/sandybridge/northbridge.c | 28 ++++++++++------------ 4 files changed, 28 insertions(+), 17 deletions(-)
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index fdc7aa6..a061b54 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -361,6 +361,10 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) return; }
+ if (res->flags & IORESOURCE_IGNORE_MTRR) { + return; + } + if (!(res->flags & IORESOURCE_CACHEABLE)) return;
diff --git a/src/include/device/device.h b/src/include/device/device.h index 1515b45..eaf84c6 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -173,17 +173,25 @@ unsigned int scan_static_bus(device_t bus, unsigned int max); void fixed_mem_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type);
+ +/* It is the caller's responsibility to adjust regions such that ram_resource() + * and mmio_resource() do not overlap. + * + * Current MTRR setup creates exclusive uncacheable holes for uma_resource() + * only and these are allowed to overlap any ram_resource(). This approach + * is used for all UMA except Intel Sandy/IvyBridge. + */ #define ram_resource(dev, idx, basek, sizek) \ fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE)
#define bad_ram_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_CACHEABLE ) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR)
#define uma_resource(dev, idx, basek, sizek) \ fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_UMA_FB)
#define mmio_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR)
void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); diff --git a/src/include/device/resource.h b/src/include/device/resource.h index e667f91..c28ada5 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -21,6 +21,7 @@ */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ #define IORESOURCE_UMA_FB 0x00100000 /* UMA framebuffer */ +#define IORESOURCE_IGNORE_MTRR 0x00200000 /* The resource does not affect MTRR setup. */
#define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index bfb2166..0df85a7 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -63,19 +63,6 @@ static const int legacy_hole_size_k = 384;
int add_northbridge_resources(struct lb_memory *mem) { - lb_add_memory_range(mem, LB_MEM_RESERVED, - legacy_hole_base_k * 1024, legacy_hole_size_k * 1024); - -#if CONFIG_CHROMEOS_RAMOOPS - lb_add_memory_range(mem, LB_MEM_RESERVED, - CONFIG_CHROMEOS_RAMOOPS_RAM_START, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE); -#endif - - /* Required for SandyBridge sighting 3715511 */ - lb_add_memory_range(mem, LB_MEM_RESERVED, 0x20000000, 0x00200000); - lb_add_memory_range(mem, LB_MEM_RESERVED, 0x40000000, 0x00200000); - return 0; }
@@ -126,7 +113,7 @@ static void add_fixed_resources(struct device *dev, int index)
printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " "size=0x%llx\n", uma_memory_base, uma_memory_size); - resource = new_resource(dev, index); + resource = new_resource(dev, index++); resource->base = (resource_t) uma_memory_base; resource->size = (resource_t) uma_memory_size; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | @@ -139,12 +126,23 @@ static void add_fixed_resources(struct device *dev, int index) if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index+1); + resource = new_resource(dev, index++); resource->base = (resource_t) pcie_config_base; resource->size = (resource_t) pcie_config_size; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } + + mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); + +#if CONFIG_CHROMEOS_RAMOOPS + mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); +#endif + + /* Required for SandyBridge sighting 3715511 */ + bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); + bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); }
static void pci_domain_set_resources(device_t dev)
-
Kyösti Mälkki