hi!
today i tried the flashrom utility from coreboot-v2 svn trunk. this is the output: ----- fin@xiix:~$ sudo flashrom Calibrating delay loop... OK. Can't mmap memory using /dev/mem: Invalid argument -----
therefore i want to ask you if my chipset is unsupported. maybe you can shed some light on this.
my system: asus p5q debian/gnu linux (sid) (debian standard kernel 2.6.26.1, customized vanilla 2.6.28-rc8)
i tested it with both kernels and got same results.
also i wanted to ask if it's possible to support this motherboard if i help you and test stuff and so on. i have some knownledge in c/c++ and very little knownledge in programing drivers (linux). also i'm eager to learn.
regards thomas prochaska
Hi Thomas!
Thomas Prochaska wrote:
today i tried the flashrom utility from coreboot-v2 svn trunk. this is the output:
fin@xiix:~$ sudo flashrom Calibrating delay loop... OK. Can't mmap memory using /dev/mem: Invalid argument
therefore i want to ask you if my chipset is unsupported. maybe you can shed some light on this.
my system: asus p5q debian/gnu linux (sid) (debian standard kernel 2.6.26.1, customized vanilla 2.6.28-rc8)
i tested it with both kernels and got same results.
Please check that CONFIG_STRICT_DEVMEM is not set in your kernel configuration. If it is set (I believe at least debian has it set) flashrom can not work properly.
also i wanted to ask if it's possible to support this motherboard if i help you and test stuff and so on.
Yes, it should be possible to support your board. ASUS has had tricky board enables in the past, but hopefully yours isn't one of them.
//Peter
On Sun, Dec 21, 2008 at 7:52 PM, Peter Stuge peter@stuge.se wrote:
Hi Thomas!
Thomas Prochaska wrote:
today i tried the flashrom utility from coreboot-v2 svn trunk. this is the output:
fin@xiix:~$ sudo flashrom Calibrating delay loop... OK. Can't mmap memory using /dev/mem: Invalid argument
therefore i want to ask you if my chipset is unsupported. maybe you can shed some light on this.
my system: asus p5q debian/gnu linux (sid) (debian standard kernel 2.6.26.1, customized vanilla 2.6.28-rc8)
i tested it with both kernels and got same results.
Please check that CONFIG_STRICT_DEVMEM is not set in your kernel configuration. If it is set (I believe at least debian has it set) flashrom can not work properly.
Debian testing at least does not, but his customized vanilla kernel might ;)
-Corey
also i wanted to ask if it's possible to support this motherboard if i help you and test stuff and so on.
Yes, it should be possible to support your board. ASUS has had tricky board enables in the past, but hopefully yours isn't one of them.
//Peter
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Peter Stuge wrote:
Hi Thomas!
Thomas Prochaska wrote:
today i tried the flashrom utility from coreboot-v2 svn trunk. this is the output:
fin@xiix:~$ sudo flashrom Calibrating delay loop... OK. Can't mmap memory using /dev/mem: Invalid argument
therefore i want to ask you if my chipset is unsupported. maybe you can shed some light on this.
my system: asus p5q debian/gnu linux (sid) (debian standard kernel 2.6.26.1, customized vanilla 2.6.28-rc8)
i tested it with both kernels and got same results.
Please check that CONFIG_STRICT_DEVMEM is not set in your kernel configuration. If it is set (I believe at least debian has it set) flashrom can not work properly.
also i wanted to ask if it's possible to support this motherboard if i help you and test stuff and so on.
Yes, it should be possible to support your board. ASUS has had tricky board enables in the past, but hopefully yours isn't one of them.
//Peter
hi!
ok, i found the problem. i hadn't set CONFIG_STRICT_DEVMEM but i had x86-pat enabled. this was the problem. with the nopat kernel boot option it produces this output: ----- xiix:~# flashrom -V Calibrating delay loop... 855M loops per second, 100 myus = 200 us. OK. No coreboot table found. Found chipset "Intel ICH10R", enabling flash write... BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1
Root Complex Register Block address = 0xfed1c000 GCS = 0x1464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x00: 0x1fff (HSFS) FLOCKDN 1, FDV 1, FDOPSS 0, SCIP 0, BERASE 0, AEL 0, FCERR 0, FDONE 0 0x50: 0x00000202 (FRAP) BMWAG 0, BMRAG 0, BRWA 2, BRRA 2 0x54: 0x00001fff (FREG0) 0x58: 0x00001fff (FREG1) 0x5C: 0x00001fff (FREG2) 0x60: 0x00001fff (FREG3) 0x64: 0x00001fff (FREG4) 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0xB0: 0x00000000 (FDOC) SPI Read Configuration: prefetching disabled, caching enabled, OK. Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0x4d, id2 0x5a, id1 parity violation Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0x4d, id2 0x5a, id1 parity violation Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0xa3, id2 0x51 Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0xa3, id2 0x51 Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0x4d, id2 0x5a, id1 parity violation Probing for Atmel AT25DF021, 256 KB: Segmentation fault -----
is that a problem or just because i haven't provided an image to write.
thomas
Thomas Prochaska wrote:
ok, i found the problem. i hadn't set CONFIG_STRICT_DEVMEM but i had x86-pat enabled. this was the problem.
Aha! Good find.
with the nopat kernel boot option it produces this output:
xiix:~# flashrom -V
..
Probing for Atmel AT25DF021, 256 KB: Segmentation fault
is that a problem or just because i haven't provided an image to write.
This is a bug in the ICH SPI driver that must have been introduced in the last few commits. Unfortunately I'm not completely familiar with that code.
It would be helpful if you could provide a backtrace, please compile flashrom with debugging enabled (add -g to CFLAGS and LDFLAGS, and comment out the STRIP on line 43 in Makefile) and then run flashrom in gdb:
# gdb ./flashrom .. (gdb) r -V .. crash (gdb) bt
and post the output.
It would also be helpful if you could update (downgrade really) to revisions 3809 and 3804 in turn, to see if they work better. Run:
svn up -r 3809
Thanks!
//Peter
Peter Stuge wrote:
Thomas Prochaska wrote:
ok, i found the problem. i hadn't set CONFIG_STRICT_DEVMEM but i had x86-pat enabled. this was the problem.
Aha! Good find.
with the nopat kernel boot option it produces this output:
xiix:~# flashrom -V
..
Probing for Atmel AT25DF021, 256 KB: Segmentation fault
is that a problem or just because i haven't provided an image to write.
This is a bug in the ICH SPI driver that must have been introduced in the last few commits. Unfortunately I'm not completely familiar with that code.
It would be helpful if you could provide a backtrace, please compile flashrom with debugging enabled (add -g to CFLAGS and LDFLAGS, and comment out the STRIP on line 43 in Makefile) and then run flashrom in gdb:
# gdb ./flashrom .. (gdb) r -V .. crash (gdb) bt
and post the output.
It would also be helpful if you could update (downgrade really) to revisions 3809 and 3804 in turn, to see if they work better. Run:
svn up -r 3809
Thanks!
//Peter
so, thanks for your advice. gdb produced following output: ---- fin@xiix:~$ sudo gdb flashrom GNU gdb 6.8-debian Copyright (C) 2008 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later http://gnu.org/licenses/gpl.html This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "x86_64-linux-gnu"... (gdb) r -V Starting program: /usr/local/sbin/flashrom -V Calibrating delay loop... 855M loops per second, 100 myus = 200 us. OK. No coreboot table found. Found chipset "Intel ICH10R", enabling flash write... BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1
Root Complex Register Block address = 0xfed1c000 GCS = 0x1464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x00: 0x1fff (HSFS) FLOCKDN 1, FDV 1, FDOPSS 0, SCIP 0, BERASE 0, AEL 0, FCERR 0, FDONE 0 0x50: 0x00000202 (FRAP) BMWAG 0, BMRAG 0, BRWA 2, BRRA 2 0x54: 0x00001fff (FREG0) 0x58: 0x00001fff (FREG1) 0x5C: 0x00001fff (FREG2) 0x60: 0x00001fff (FREG3) 0x64: 0x00001fff (FREG4) 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0xB0: 0x00000000 (FDOC) SPI Read Configuration: prefetching disabled, caching enabled, OK. Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0x4d, id2 0x5a, id1 parity violation Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0x4d, id2 0x5a, id1 parity violation Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0xa3, id2 0x51 Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0xa3, id2 0x51 Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0x4d, id2 0x5a, id1 parity violation Probing for Atmel AT25DF021, 256 KB: Program received signal SIGSEGV, Segmentation fault. 0x0000000000408fae in ich_spi_command (writecnt=1, readcnt=3, writearr=0x7fff772399cf "\237", readarr=0x7fff772399e0 "M") at ichspi.c:763 763 if ((curopcodes->opcode[a]).opcode == cmd) { (gdb) bt #0 0x0000000000408fae in ich_spi_command (writecnt=1, readcnt=3, writearr=0x7fff772399cf "\237", readarr=0x7fff772399e0 "M") at ichspi.c:763 #1 0x0000000000407fdc in spi_rdid (readarr=0x7fff772399e0 "M", bytes=159) at spi.c:59 #2 0x0000000000408027 in probe_spi_rdid_generic (flash=0x610a70, bytes=159) at spi.c:108 #3 0x00000000004066b8 in probe_flash (first_flash=0x610860, force=0) at flashrom.c:149 #4 0x0000000000406aec in main (argc=2, argv=0x7fff77239c58) at flashrom.c:468 (gdb) ----
i also tried revision 3809 and 3804, both worked and produced following output: ---- Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH10R", enabling flash write... OK. Found chip "Macronix MX25L8005" (1024 KB) at physical address 0xfff00000. No operations were specified. ----
-- thomas
Peter Stuge wrote:
Thomas Prochaska wrote:
ok, i found the problem. i hadn't set CONFIG_STRICT_DEVMEM but i had x86-pat enabled. this was the problem.
Aha! Good find.
with the nopat kernel boot option it produces this output:
xiix:~# flashrom -V
..
Probing for Atmel AT25DF021, 256 KB: Segmentation fault
is that a problem or just because i haven't provided an image to write.
This is a bug in the ICH SPI driver that must have been introduced in the last few commits. Unfortunately I'm not completely familiar with that code.
It would be helpful if you could provide a backtrace, please compile flashrom with debugging enabled (add -g to CFLAGS and LDFLAGS, and comment out the STRIP on line 43 in Makefile) and then run flashrom in gdb:
# gdb ./flashrom .. (gdb) r -V .. crash (gdb) bt
and post the output.
It would also be helpful if you could update (downgrade really) to revisions 3809 and 3804 in turn, to see if they work better. Run:
svn up -r 3809
Thanks!
//Peter
ok, thanks for your advice. here's the gdb output: ---- fin@xiix:~$ sudo gdb flashrom GNU gdb 6.8-debian Copyright (C) 2008 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later http://gnu.org/licenses/gpl.html This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "x86_64-linux-gnu"... (gdb) r -V Starting program: /usr/local/sbin/flashrom -V Calibrating delay loop... 855M loops per second, 100 myus = 200 us. OK. No coreboot table found. Found chipset "Intel ICH10R", enabling flash write... BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1
Root Complex Register Block address = 0xfed1c000 GCS = 0x1464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x00: 0x1fff (HSFS) FLOCKDN 1, FDV 1, FDOPSS 0, SCIP 0, BERASE 0, AEL 0, FCERR 0, FDONE 0 0x50: 0x00000202 (FRAP) BMWAG 0, BMRAG 0, BRWA 2, BRRA 2 0x54: 0x00001fff (FREG0) 0x58: 0x00001fff (FREG1) 0x5C: 0x00001fff (FREG2) 0x60: 0x00001fff (FREG3) 0x64: 0x00001fff (FREG4) 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0xB0: 0x00000000 (FDOC) SPI Read Configuration: prefetching disabled, caching enabled, OK. Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0x4d, id2 0x5a, id1 parity violation Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0x4d, id2 0x5a, id1 parity violation Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0xa3, id2 0x51 Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0xa3, id2 0x51 Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0x4d, id2 0x5a, id1 parity violation Probing for Atmel AT25DF021, 256 KB: Program received signal SIGSEGV, Segmentation fault. 0x0000000000408fae in ich_spi_command (writecnt=1, readcnt=3, writearr=0x7fff772399cf "\237", readarr=0x7fff772399e0 "M") at ichspi.c:763 763 if ((curopcodes->opcode[a]).opcode == cmd) { (gdb) bt #0 0x0000000000408fae in ich_spi_command (writecnt=1, readcnt=3, writearr=0x7fff772399cf "\237", readarr=0x7fff772399e0 "M") at ichspi.c:763 #1 0x0000000000407fdc in spi_rdid (readarr=0x7fff772399e0 "M", bytes=159) at spi.c:59 #2 0x0000000000408027 in probe_spi_rdid_generic (flash=0x610a70, bytes=159) at spi.c:108 #3 0x00000000004066b8 in probe_flash (first_flash=0x610860, force=0) at flashrom.c:149 #4 0x0000000000406aec in main (argc=2, argv=0x7fff77239c58) at flashrom.c:468 (gdb) ----
i checked with revision 3809 and 3804 and both should work. both produced following output: ---- Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH10R", enabling flash write... OK. Found chip "Macronix MX25L8005" (1024 KB) at physical address 0xfff00000. No operations were specified. ----
-- thomas
Thomas Prochaska wrote:
Program received signal SIGSEGV, Segmentation fault. 0x0000000000408fae in ich_spi_command (writecnt=1, readcnt=3, writearr=0x7fff772399cf "\237", readarr=0x7fff772399e0 "M") at ichspi.c:763 763 if ((curopcodes->opcode[a]).opcode == cmd) { (gdb) bt #0 0x0000000000408fae in ich_spi_command (writecnt=1, readcnt=3, writearr=0x7fff772399cf "\237", readarr=0x7fff772399e0 "M") at ichspi.c:763
Ok.
i checked with revision 3809 and 3804 and both should work.
Looks good. Ok. Please go back to trunk HEAD (svn up -r HEAD) and try applying this patch.
//Peter
Peter Stuge wrote:
Thomas Prochaska wrote:
Program received signal SIGSEGV, Segmentation fault. 0x0000000000408fae in ich_spi_command (writecnt=1, readcnt=3, writearr=0x7fff772399cf "\237", readarr=0x7fff772399e0 "M") at ichspi.c:763 763 if ((curopcodes->opcode[a]).opcode == cmd) { (gdb) bt #0 0x0000000000408fae in ich_spi_command (writecnt=1, readcnt=3, writearr=0x7fff772399cf "\237", readarr=0x7fff772399e0 "M") at ichspi.c:763
Ok.
i checked with revision 3809 and 3804 and both should work.
Looks good. Ok. Please go back to trunk HEAD (svn up -r HEAD) and try applying this patch.
//Peter
k, i checked, that did it. thanks.
-- thomas
On Mon, Dec 22, 2008 at 12:10 PM, Peter Stuge peter@stuge.se wrote:
Thomas Prochaska wrote:
Program received signal SIGSEGV, Segmentation fault. 0x0000000000408fae in ich_spi_command (writecnt=1, readcnt=3, writearr=0x7fff772399cf "\237", readarr=0x7fff772399e0 "M") at ichspi.c:763 763 if ((curopcodes->opcode[a]).opcode == cmd) { (gdb) bt #0 0x0000000000408fae in ich_spi_command (writecnt=1, readcnt=3, writearr=0x7fff772399cf "\237", readarr=0x7fff772399e0 "M") at ichspi.c:763
Ok.
I felt nervous when I read here.
i checked with revision 3809 and 3804 and both should work.
Looks good. Ok. Please go back to trunk HEAD (svn up -r HEAD) and try applying this patch.
Having read the patch, I realized that my deletion of opcode programming affected both ICH7 and 9, but I only initialized opcodes for ICH7.
On Mon, Dec 22, 2008 at 12:43 PM, Thomas Prochaska dev@duffd.net wrote:
k, i checked, that did it. thanks.
Luckily it is a minor mistake and easy to fix.
Thanks for the patch, Peter.
yu ning