Author: uwe Date: 2008-03-13 15:16:38 +0100 (Thu, 13 Mar 2008) New Revision: 642
Modified: coreboot-v3/northbridge/amd/geodelx/domain coreboot-v3/northbridge/amd/geodelx/geodelink.h coreboot-v3/northbridge/amd/geodelx/geodelx.c coreboot-v3/northbridge/amd/geodelx/geodelxinit.c coreboot-v3/northbridge/amd/geodelx/grphinit.c coreboot-v3/northbridge/amd/geodelx/raminit.c coreboot-v3/northbridge/amd/geodelx/vsmsetup.c Log: Cosmetic fixes, coding style issues, added comments (trivial).
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: coreboot-v3/northbridge/amd/geodelx/domain =================================================================== --- coreboot-v3/northbridge/amd/geodelx/domain 2008-03-13 13:31:16 UTC (rev 641) +++ coreboot-v3/northbridge/amd/geodelx/domain 2008-03-13 14:16:38 UTC (rev 642) @@ -22,7 +22,7 @@ { device_operations = "geodelx_north_domain";
- /* Video RAM has to be in 2MB chunks. */ - geode_video_mb = "0"; + /* Video RAM has to be in 2MB chunks. */ + geode_video_mb = "0"; };
Modified: coreboot-v3/northbridge/amd/geodelx/geodelink.h =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelink.h 2008-03-13 13:31:16 UTC (rev 641) +++ coreboot-v3/northbridge/amd/geodelx/geodelink.h 2008-03-13 14:16:38 UTC (rev 642) @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#ifndef GEODELINK_H -#define GEODELINK_H +#ifndef NORTHBRIDGE_AMD_GEODE_GEODELINK_H +#define NORTHBRIDGE_AMD_GEODE_GEODELINK_H
struct gliutable { unsigned long desc_name; @@ -75,4 +75,4 @@
static const struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
-#endif /* GEODELINK_H */ +#endif /* NORTHBRIDGE_AMD_GEODE_GEODELINK_H */
Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-03-13 13:31:16 UTC (rev 641) +++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-03-13 14:16:38 UTC (rev 642) @@ -43,7 +43,6 @@ { }
- /** * TODO. * @@ -67,8 +66,8 @@ systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8); systop += 4 * 1024; /* 4K */ } else { - systop = - (((sizeram() - nb_dm->geode_video_mb) * 1024) - SMM_SIZE) * 1024; + systop = (((sizeram() - nb_dm->geode_video_mb) * 1024) + - SMM_SIZE) * 1024; }
return systop; @@ -82,10 +81,7 @@ */ static void geodelx_northbridge_init(struct device *dev) { - /* struct msr msr; */ - printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); - enable_shadow(dev); }
@@ -162,7 +158,7 @@ ram_resource(dev, idx++, 0, 640); /* 1 MB .. (Systop - 1 MB) (in KB) */ ram_resource(dev, idx++, 1024, - (get_systop(nb_dm)/1024) - 1024); + (get_systop(nb_dm) / 1024) - 1024); }
phase4_assign_resources(&dev->link[0]); @@ -189,7 +185,7 @@
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
-// northbridge_init_early(); + /* northbridge_init_early(); */ chipsetinit();
printk(BIOS_SPEW, "Before VSA:\n"); @@ -198,7 +194,7 @@ do_vsmbios(); printk(BIOS_SPEW, "After VSA:\n"); /* print_conf(); */ -printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", nb_dm->geode_video_mb); + printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", nb_dm->geode_video_mb); graphics_init((u8)nb_dm->geode_video_mb); pci_set_method(dev); } @@ -254,9 +250,10 @@ .ops_pci_bus = &pci_cf8_conf1, };
-/** Operations for when the northbridge is running a PCI device. */ -/** Note that phase3 scan is done in the domain, - * and MUST NOT be done here too +/** + * Operations for when the northbridge is running a PCI device. + * + * Note that phase3 scan is done in the domain, and MUST NOT be done here too. */ struct device_operations geodelx_north_pci = { .id = {.type = DEVICE_ID_PCI,
Modified: coreboot-v3/northbridge/amd/geodelx/geodelxinit.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelxinit.c 2008-03-13 13:31:16 UTC (rev 641) +++ coreboot-v3/northbridge/amd/geodelx/geodelxinit.c 2008-03-13 14:16:38 UTC (rev 642) @@ -25,7 +25,6 @@ #include <amd_geodelx.h> #include "geodelink.h"
- static struct msrinit clock_gating_default[] = { {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, @@ -204,6 +203,7 @@ static void SMMGL1Init(const struct gliutable *gl) { struct msr msr; + printk(BIOS_DEBUG, "%s:\n", __FUNCTION__);
msr.hi = gl->hi; @@ -219,9 +219,10 @@ }
/** - * Set up all GeodeLink interfaces. Iterate over the table until done. + * Set up all GeodeLink interfaces. * - * Case out on the link type, and call the appropriate function. + * Iterate over the table until done. Case out on the link type, + * and call the appropriate function. * * @param gl A GeodeLink table descriptor. */ @@ -288,7 +289,8 @@ * translates to a base of 0x00100000 and top of 0xffbf0000 * base of 1M and top of around 256M. */ - /* we have to create a page-aligned (4KB page) address + + /* We have to create a page-aligned (4KB page) address * for base and top. * So we need a high page aligned addresss (pah) and * low page aligned address (pal) pah is from msr.hi @@ -319,10 +321,11 @@ msr.lo, msr.hi); wrmsr(GLPCI_RC2, msr);
- /* This is done elsewhere already, but it does no harm to do + /* + * This is done elsewhere already, but it does no harm to do * it more than once. - */ - /* Write serialize memory hole to PCI. Need to to unWS when + * + * Write serialize memory hole to PCI. Need to to unWS when * something is shadowed regardless of cachablility. */ msr.lo = 0x021212121; /* Cache disabled and write serialized. */ @@ -708,7 +711,6 @@ printk(BIOS_DEBUG, "L2 cache enabled\n"); }
- /** * Set up all LX cache registers, L1, L2, and x86. */ @@ -767,8 +769,8 @@
/* Set ROM cache properties for runtime. */ msr = rdmsr(CPU_RCONF_DEFAULT); - msr.hi &= ~(0xFF << 24); // clear ROMRC - msr.hi |= ROMRC_RCONF_SAFE << 24; // set WS, CD, WP + msr.hi &= ~(0xFF << 24); /* Clear ROMRC. */ + msr.hi |= ROMRC_RCONF_SAFE << 24; /* Set WS, CD, WP. */ wrmsr(CPU_RCONF_DEFAULT, msr); }
Modified: coreboot-v3/northbridge/amd/geodelx/grphinit.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/grphinit.c 2008-03-13 13:31:16 UTC (rev 641) +++ coreboot-v3/northbridge/amd/geodelx/grphinit.c 2008-03-13 14:16:38 UTC (rev 642) @@ -23,9 +23,11 @@ #include <console.h> #include <statictree.h>
- /* - * This function mirrors the Graphics_Init routine in GeodeROM. - */ +/** + * This function mirrors the Graphics_Init routine in GeodeROM. + * + * @param video_mb Size of the video RAM in 2 MB chunks. + */ void graphics_init(u8 video_mb) { u16 wClassIndex, wData, res; @@ -34,7 +36,7 @@ printk(BIOS_DEBUG, "Graphics init...\n");
/* Call SoftVG with the main configuration parameters. */ - /* NOTE: SoftVG expects the memory size to be given in 2MB blocks */ + /* NOTE: SoftVG expects the memory size to be given in 2MB blocks. */
wClassIndex = (VRC_VG << 8) + VG_CONFIG;
@@ -48,13 +50,12 @@ * PLL Reference Clock Bypass(0) 0, Default */
- /* Video RAM has to be given in 2MB chunks - * the value is read @ 7:1 (looks like video_mb & ~1) - * so we can add the real value in megabytes. + /* Video RAM has to be given in 2MB chunks. + * The value is read @ 7:1 (looks like video_mb & ~1) + * so we can add the real value in megabytes. */ - - wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | - VG_CFG_DSCRT | (video_mb & VG_MEM_MASK); + wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | + VG_CFG_DSCRT | (video_mb & VG_MEM_MASK); vr_write(wClassIndex, wData);
res = vr_read(wClassIndex);
Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-03-13 13:31:16 UTC (rev 641) +++ coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-03-13 14:16:38 UTC (rev 642) @@ -36,17 +36,15 @@ u8 spd_read_byte(u16 device, u8 address);
/** - * Halt and Catch Fire. Print an error, then loop, sending NULLs on serial port, - * to ensure the message is visible. - * + * Halt and Catch Fire. Print an error, then loop, sending NULLs on + * serial port, to ensure the message is visible. */ - void hcf(void) { printk(BIOS_EMERG, "DIE\r\n"); - /* this guarantees we flush the UART fifos (if any) and also - * ensures that things, in general, keep going so no debug output - * is lost + + /* This guarantees we flush the UART FIFOs (if any) and also ensures + * that things, in general, keep going so no debug output is lost. */ while (1) printk(BIOS_EMERG, "\r"); @@ -97,12 +95,12 @@ } dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
- /*; Field: DIMM size - *; EEPROM byte usage: (3) Number of Row Addresses - *; (4) Number of Column Addresses - *; (5) Number of DIMM Banks - *; (31) Module Bank Density - *; Size = Module Density * Module Banks + /* Field: DIMM size + * EEPROM byte usage: (3) Number of Row Addresses + * (4) Number of Column Addresses + * (5) Number of DIMM Banks + * (31) Module Bank Density + * Size = Module Density * Module Banks */ banner(BIOS_DEBUG, "SPDNUMROWS");
@@ -228,7 +226,7 @@ printk(BIOS_DEBUG, "ddr max speed is %d\n", speed); /* Current speed > max speed? */ if (geode_link_speed() > speed) { - printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed\n"); + printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed.\n"); post_code(POST_PLL_MEM_FAIL); hlt(); } @@ -562,7 +560,7 @@ { struct msr msr;
- /* Set Timing Control */ + /* Set Timing Control. */ msr = rdmsr(MC_CF1017_DATA); msr.lo &= ~(7 << CF1017_LOWER_RD_TMG_CTL_SHIFT); if (geode_link_speed() < 334) @@ -571,7 +569,7 @@ msr.lo |= (4 << CF1017_LOWER_RD_TMG_CTL_SHIFT); wrmsr(MC_CF1017_DATA, msr);
- /* Set Refresh Staggering */ + /* Set Refresh Staggering. */ msr = rdmsr(MC_CF07_DATA); msr.lo &= ~0xF0; msr.lo |= 0x40; /* Set refresh to 4 SDRAM clocks. */ @@ -610,8 +608,8 @@ /* Check that the memory is not overclocked. */ check_ddr_max(dimm0, dimm1);
- /* Size the DIMMS. - * This is gross. It is an artifact of our move to parametes instead of + /* Size the DIMMs. + * This is gross. It is an artifact of our move to parameters instead of * #defines. FIXME! The fix is trivial but I want to see it work first. */ post_code(POST_MEM_SETUP3); @@ -623,7 +621,7 @@ post_code(POST_MEM_SETUP5); set_cas(dimm0, dimm1);
- /* Set all the other latencies here (tRAS, tRP...). */ + /* Set all the other latencies here (tRAS, tRP, ...). */ set_latencies(dimm0, dimm1);
/* Set Extended Mode Registers. */ @@ -788,9 +786,8 @@ *ptr = (unsigned long)i; }
- /* SWAPSiF for PBZ 4112 (Errata 34) - * Check for failed DLL settings now that we have done a - * memory write. + /* SWAPSiF for PBZ 4112 (Errata 34). + * Check for failed DLL settings now that we have done a memory write. */ msr = rdmsr(GLCP_DELAY_CONTROLS); if ((msr.lo & 0x7FF) == 0x104) { @@ -798,7 +795,7 @@ * count flag (depending on where it counts from etc). */
- /* The we are about to perform clears the PM_SSC + /* The operation we are about to perform clears the PM_SSC * register in the CS5536 so will need to store the S3 * resume flag in NVRAM otherwise it would do a normal boot. */
Modified: coreboot-v3/northbridge/amd/geodelx/vsmsetup.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/vsmsetup.c 2008-03-13 13:31:16 UTC (rev 641) +++ coreboot-v3/northbridge/amd/geodelx/vsmsetup.c 2008-03-13 14:16:38 UTC (rev 642) @@ -1,27 +1,30 @@ /* - * Copyright (C) 2000 Erik Arjan Hendriks - * Copyright (C) 2000 Scyld Computing Corporation - * Copyright (C) 2001 University of California. LA-CC Number 01-67. - * Copyright (C) 2005 Nick.Barker9@btinternet.com - * Copyright (C) 2007 coresystems GmbH + * This file is part of the coreboot project. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2000 Erik Arjan Hendriks + * Copyright (C) 2000 Scyld Computing Corporation + * Copyright (C) 2001 University of California. LA-CC Number 01-67. + * Copyright (C) 2005 Nick.Barker9@btinternet.com + * Copyright (C) 2007 coresystems GmbH * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * * LA-CC is the Los Alamos Control and Compliance Number, see also: * http://supply.lanl.gov/property/customs/eximguide/default.shtml */ + #include <types.h> #include <console.h> #include <device/device.h> @@ -31,82 +34,93 @@ #include <amd_geodelx.h> #include <lar.h>
-#define VSA2_BUFFER 0x60000 +#define VSA2_BUFFER 0x60000 #define VSA2_ENTRY_POINT 0x60020
- -/* The address arguments to this function are PHYSICAL ADDRESSES */ +/** + * TODO. + * + * The address arguments to this function are PHYSICAL ADDRESSES! + * + * @param smm TODO. + * @param sysm TODO. + */ static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm) { u16 entryHi = (VSA2_ENTRY_POINT & 0xffff0000) >> 4; u16 entryLo = (VSA2_ENTRY_POINT & 0xffff);
__asm__ __volatile__( - // paranoia -- does ecx get saved? not sure. This is - // the easiest safe thing to do. + /* Paranoia -- does ecx get saved? not sure. This is + * the easiest safe thing to do. + */ " pushal \n" - /* save the stack */ + /* Save the stack. */ " mov %%esp, __stack \n" " jmp 1f \n" "__stack: .long 0 \n" "1:\n" - /* get devfn into %%ecx */ + /* Get devfn into %%ecx. */ " movl %%esp, %%ebp \n" - /* Get the smm and sysm args into ecx and edx */ + /* Get the smm and sysm args into ecx and edx. */ " movl %0, %%ecx \n" " movl %1, %%edx \n" - /* load 'our' gdt */ + /* Load 'our' gdt. */ " lgdt %%cs:__mygdtaddr \n" - /* This configures CS properly for real mode. */ + /* This configures CS properly for real mode. */ " ljmp $0x28, $__rms_16bit\n" "__rms_16bit: \n" " .code16 \n" /* 16 bit code from here on... */ - /* Load the segment registers w/ properly configured segment - * descriptors. They will retain these configurations (limits, - * writability, etc.) once protected mode is turned off. */ + /* Load the segment registers with properly configured segment + * descriptors. They will retain these configurations (limits, + * writability, etc.) once protected mode is turned off. + */ " mov $0x30, %%ax \n" " mov %%ax, %%ds \n" " mov %%ax, %%es \n" " mov %%ax, %%fs \n" " mov %%ax, %%gs \n" " mov %%ax, %%ss \n" - /* Turn off protection (bit 0 in CR0) */ + /* Turn off protection (bit 0 in CR0). */ " movl %%cr0, %%eax \n" " andl $0xFFFFFFFE, %%eax \n" " movl %%eax, %%cr0 \n" - /* Now really going into real mode */ + /* Now really going into real mode. */ " ljmp $0, $__rms_real\n" "__rms_real: \n"
- /* put the stack at the end of page zero. - * that way we can easily share it between real and protected, - * since the 16-bit ESP at segment 0 will work for any case. + /* Put the stack at the end of page zero. + * That way we can easily share it between real and protected, + * since the 16-bit ESP at segment 0 will work for any case. */
- /* Setup a stack */ + /* Setup a stack. */ " mov $0x0, %%ax \n" " mov %%ax, %%ss \n" " movl $0x1000, %%eax \n" " movl %%eax, %%esp \n" - /* Dump zeros in the other segregs */ + /* Dump zeros in the other segregs. */ " mov %%ax, %%es \n" - /* FixMe: Big real mode for gs, fs? */ + /* FIXME: Big real mode for gs, fs? */ " mov %%ax, %%fs \n" " mov %%ax, %%gs \n" " mov $0x40, %%ax \n" " mov %%ax, %%ds \n" - //" mov %%cx, %%ax \n" + /* " mov %%cx, %%ax \n" */ " movl %0, %%ecx \n" " movl %1, %%edx \n" - /* call the VSA2 entry point address */ + /* Call the VSA2 entry point address. */ " lcall %2, %3\n" - /* if we got here, just about done. - * Need to get back to protected mode */ + /* If we got here, just about done. + * Need to get back to protected mode. + */ " movl %%cr0, %%eax \n" " orl $0x0000001, %%eax\n" /* PE = 1 */ " movl %%eax, %%cr0 \n" - /* Now that we are in protected mode jump to a 32 bit code segment. */ + /* Now that we are in protected mode, + * jump to a 32 bit code segment. + */ " data32 ljmp $0x10, $vsmrestart\n" "vsmrestart:\n" " .code32\n" @@ -116,7 +130,7 @@ " mov %%ax, %%fs \n" " mov %%ax, %%gs \n" " mov %%ax, %%ss \n" - /* restore proper gdt */ + /* Restore proper gdt. */ " lgdt %%cs:gdtarg \n" ".globl vsm_exit \n" "vsm_exit: \n" @@ -129,7 +143,7 @@ __asm__(".text\n" "real_mode_switch_end:\n"); extern char real_mode_switch_end[];
-// andrei: some VSA virtual register helpers: raw read and MSR read +/* andrei: Some VSA virtual register helpers: raw read and MSR read. */
u32 VSA_vrRead(u16 classIndex) { @@ -167,46 +181,44 @@ { unsigned char *buf; int i; - struct mem_file archive; - struct mem_file file; + struct mem_file archive, file;
printk(BIOS_ERR, "do_vsmbios\n"); - /* clear vsm bios data area */ - for (i = 0x400; i < 0x500; i++) { + /* Clear VSM BIOS data area. */ + for (i = 0x400; i < 0x500; i++) *(volatile unsigned char *)i = 0; - } init_archive(&archive);
- if (find_file(&archive, "blob/vsa", &file)){ + if (find_file(&archive, "blob/vsa", &file)) die("FATAL: NO VSA found!\n"); - }
- if (process_file(&file, (void *)VSA2_BUFFER)) { + if (process_file(&file, (void *)VSA2_BUFFER)) die("FATAL: Processing /blob/vsa failed\n"); - }
buf = (unsigned char *)VSA2_BUFFER; - printk(BIOS_DEBUG, "buf ilen %d real len %uld\n", file.len, file.reallen); + printk(BIOS_DEBUG, "buf ilen %d real len %uld\n", + file.len, file.reallen); printk(BIOS_DEBUG, "buf %p *buf %d buf[256k] %d\n", - buf, buf[0], buf[SMM_SIZE * 1024]); + buf, buf[0], buf[SMM_SIZE * 1024]); printk(BIOS_DEBUG, "buf[0x20] signature is %x:%x:%x:%x\n", - buf[0x20], buf[0x21], buf[0x22], buf[0x23]); - /* check for post code at start of vsainit.bin. If you don't see it, - don't bother. */ + buf[0x20], buf[0x21], buf[0x22], buf[0x23]); + /* Check for POST code at start of vsainit.bin. If you don't see it, + * don't bother. + */ if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) || (buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) { die("FATAL: no vsainit.bin signature, skipping!\n"); }
- /* ecx gets smm, edx gets sysm */ + /* ecx gets smm, edx gets sysm. */ printk(BIOS_ERR, "Call real_mode_switch_call_vsm\n"); real_mode_switch_call_vsm(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM);
- /* restart timer 1 */ + /* Restart Timer 1. */ outb(0x56, 0x43); outb(0x12, 0x41);
- // check that VSA is running OK + /* Check that VSA is running OK. */ if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE) printk(BIOS_DEBUG, "do_vsmbios: VSA2 VR signature verified\n"); else
-
svn＠coreboot.org