One7two99 via coreboot wrote:
From a newbie perspective I'd like to get this information from one or two locations:
- How to get Coreboot running (general part)
- How to flash the X230
Sure thing - and I think it's great that you are working on more concise docs!
The 1) is quite a large topic.
So you flash only the last third of the CBFS, and ignore the beginning. I think it is just luck that your system boots at all. If you used a larger payload such as a kernel then your method will likely cut the payload in half and end up writing incomplete junk to your flash.
I've followed the howto in the coreboot wiki:
Sure, but what do the steps in the howto actually mean? Why are you sure that they are correct?
honestly I was also wondering why this is working and even more, why I am skipping the first 8MB of the file.
Perfect! Please also *answer* those questions; they are important.
Honestly I am trying to understand as much as I can,
Good stuff!
I am happy to contribute to the documentation to make it easier for the next newbie who might not be interested in how his CPU works, but wants to reduce possible entry points which might break his privacy :-)
Documentation contributions are just as important as code, and again I really appreciate that you are working on this.
Sorry, I didn't mean to say study the CPU (though that's also relevant for privacy; see AMD microcode paper with modified instruction exploit to leak crypto key) - I meant study what's going on with these two flash chips, since you want to change the contents of one or both.
What do the 12 MB flash contain, what is the structure, what determines the structure, what can you change, how do you change, what *can't* you change, why, and so on.
My point is that if you want to create documentation with exact steps which can be repeated by the next newbie, then you will have to make a whole bunch of very specific decisions, so that they don't have to.
Just saying to hang in there, continue understanding.
//Peter
Hello Peter,
-------- Original Message -------- Subject: Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work Local Time: 26 September 2017 11:05 AM From: peter@stuge.se
- How to get Coreboot running (general part)
The 1) is quite a large topic.
Strangely that part seems to much easier as there is already excellent documentation available how to install all dependencies, build the toolchain. I've verified this several times by installing coreboot on a freshly installed Ubuntu 16.04.3 LTS.
I"ve followed the howto in the coreboot wiki:
Sure, but what do the steps in the howto actually mean? Why are you sure that they are correct?
I am not sure that is why I am asking :-) And I got already different answers.
honestly I was also wondering why this is working and even more, why I am skipping the first 8MB of the file.
Perfect! Please also *answer* those questions; they are important.
I good a better understanding after looking at the picture one the me_cleaner site here: https://github.com/corna/me_cleaner/wiki/External-flashing This picture shows the content of the Chip: https://camo.githubusercontent.com/3ea0ff670edb94372124ad0c36bd5e2b3c522f7e/... I got confused in the beginning as the X230 contains two chips which are see as one 12 MB chip.
As I have saved the original content of both of my chips (x230-4mb.rom and x230-8m.rom) I have already looked at the content of the 8 MB chip:
cd ~/coreboot/MyFactoryROM ifdtool -x x230_8mb.rom
will extract 4 files: flashregion_0_flashdescriptor.bin (4K) --> renamed to: descriptor.bin flashregion_1_bios.bin (4,8M) flashregion_2_intel_me.bin (5,0M)--> renamed to: me.bin flashregion_3_gbe.bin (8,0K)-- > renamed to: gbe.bin
I have verified the ME image as described here https://github.com/corna/me_cleaner/wiki/External-flashing
cd ~/coreboot/MyFactoryROM ~/me_cleaner/me_cleaner.py -c x230_8mb.rom
Full image detected The ME/TXE region goes from 0x3000 to 0x500000 Found FPT header at 0x3010 Found 23 partition(s) Found FTPR header: FTPR partition spans from 0x183000 to 0x24d000 ME/TXE firmware version 8.1.71.3608 Checking the FTPR RSA signature... VALID
Strangely the 8MB chips seems to also contains the "flashregion_1_bios.bin". I tought that the BIOS part is located on the top 4 MB Chip. I'd like to both files (4MB + 8MB) into one and use that with idftool. I tried to run idftool with --chip 1 on the extracted x230-4mb.rom but this didn't succeed.
Next step is to clean the flashregion_2_intel_me.bin (me.bin) with me_cleaner which is describe well.
QUESTION: what I am really struggling with is, is the size of the CBFS filesystem in ROM (can be set under Mainboard in coreboot make nconfig). I need a bigger CBFS to be able to run payloads but then I can't just flash the upper 4 MB chip. As such the question is: what do I need to do with the coreboot.bin after compiling to be able to flash the whole 12 MB (4 mb chip + 12 mb chip). Any help would be great here, as I am currently mainly struggling with this.
[799]
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One7two99 -
Peter Stuge