Martin Roth (martin@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1975
-gerrit
commit 1d194483b469f727f05e018797a538e7b0bf0574 Author: Martin Roth martin@se-eng.com Date: Wed Dec 5 15:50:32 2012 -0700
Fix SPI BAR special case in lpc_set_resources
There was already a special case for the SPI base address in lpc_set_resources for southbridge/amd/cimx/sb800 and southbridge/amd/agesa/hudson, but it needed to be modified to keep from killing the IMC rom during initialization. As soon as the BAR is disabled by setting the new base address, the IMC dies. The fix is to make sure it's still enabled when setting the new base address instead of setting the new address then re-enabling it.
Change the name SPIROM_BASE_ADDRESS to SPIROM_BASE_ADDRESS_REGISTER to more accurately describe what we're using.
Change-Id: I216d75b722c4332c239d487111a9880eabf59e91 Signed-off-by: Martin Roth martin@se-eng.com --- src/southbridge/amd/agesa/hudson/hudson.h | 1 + src/southbridge/amd/agesa/hudson/lpc.c | 8 +++++--- src/southbridge/amd/cimx/sb800/lpc.c | 11 +++++++---- src/southbridge/amd/cimx/sb800/lpc.h | 2 +- 4 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 28faea4..15738aa 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -56,6 +56,7 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); #define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; #define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr; +#define SPIROM_BASE_ADDRESS_REGISTER 0xA0
#ifdef __PRE_RAM__ void hudson_lpc_port80(void); diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index b56fa38..86e937e 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -23,6 +23,7 @@ #include <device/pnp.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> @@ -104,11 +105,12 @@ static void hudson_lpc_set_resources(struct device *dev) { struct resource *res;
+ /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ + res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); + res->base |= PCI_COMMAND_MEMORY; + pci_dev_set_resources(dev);
- /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ - res = find_resource(dev, 0xA0); - pci_write_config32(dev, 0xA0, res->base | 1 << 1);
}
diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index caac5b1..44dd07d 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -19,6 +19,7 @@
#include <console/console.h> #include <device/pci.h> +#include <device/pci_def.h> #include <arch/ioapic.h> #include "lpc.h" #include <arch/io.h> @@ -32,7 +33,7 @@ void lpc_read_resources(device_t dev) /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
- pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */ + pci_get_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); /* SPI ROM base address */
/* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); @@ -61,11 +62,13 @@ void lpc_set_resources(struct device *dev) struct resource *res;
printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n"); + + /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ + res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); + res->base |= PCI_COMMAND_MEMORY; + pci_dev_set_resources(dev);
- /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ - res = find_resource(dev, SPIROM_BASE_ADDRESS); - pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - End.\n"); }
diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 3d6a17a..3fc8d39 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -20,7 +20,7 @@ #ifndef _SB800_LPC_H_ #define _SB800_LPC_H_
-#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ +#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 /* SPI ROM base address */
void lpc_read_resources(device_t dev); void lpc_set_resources(device_t dev);
-
Martin Roth