Patch set updated for coreboot: e0abdbe intel/socket_BGA956: enable speedstep, CAR, MMX, SSE

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1664

-gerrit

commit e0abdbe7a68da2bf2edbae3ba141752cb577b60e
Author: Patrick Georgi 
Date:   Thu Nov 1 15:32:32 2012 +0100

intel/socket_BGA956: enable speedstep, CAR, MMX, SSE

All of these capabilities exist on all CPUs supported on
    this socket.

Change-Id: I54f34e48e34bb6ab5b9954ab7ece8c2c3a1a8e67
    Signed-off-by: Patrick Georgi 
---
 src/cpu/intel/socket_BGA956/Kconfig      | 15 +++++++++++++++
 src/cpu/intel/socket_BGA956/Makefile.inc |  1 +
 src/mainboard/intel/eagleheights/Kconfig |  8 --------
 3 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig
index a764348..40f82af 100644
--- a/src/cpu/intel/socket_BGA956/Kconfig
+++ b/src/cpu/intel/socket_BGA956/Kconfig
@@ -1,3 +1,18 @@
 config CPU_INTEL_SOCKET_BGA956
    bool
    select CPU_INTEL_MODEL_1067X
+	select CACHE_AS_RAM
+	select MMX
+	select SSE
+
+if CPU_INTEL_SOCKET_BGA956
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffaf8000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+
+endif
diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc
index a290e69..f93fa00 100644
--- a/src/cpu/intel/socket_BGA956/Makefile.inc
+++ b/src/cpu/intel/socket_BGA956/Makefile.inc
@@ -7,6 +7,7 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
+subdirs-y += ../speedstep

# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
 cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig
index 7722ad2..00ef377 100644
--- a/src/mainboard/intel/eagleheights/Kconfig
+++ b/src/mainboard/intel/eagleheights/Kconfig
@@ -27,14 +27,6 @@ config MMCONF_BASE_ADDRESS
    hex
    default 0xe0000000

-config DCACHE_RAM_BASE
-	hex
-	default 0xffdf8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x8000
-
 config MAINBOARD_PART_NUMBER
    string
    default "EagleHeights"