[v2] r4147 - in trunk/coreboot-v2/src/mainboard: a-trend/atc-6220 a-trend/atc-6240 abit/be6-ii_v2_0 advantech/pcm-5820 amd/db800 amd/dbm690t amd/norwich amd/pistachio amd/rumba amd/serengeti_cheetah amd/serengeti_cheetah_fam10 artecgroup/dbe61 asi/mb_5blgp asi/mb_5blmp asus/a8n_e asus/a8v-e_se asus/mew-am asus/mew-vm asus/p2b asus/p2b-d asus/p2b-ds asus/p2b-f asus/p3b-f axus/tc320 azza/pt-6ibd bcom/winnet100 bcom/winnetp680 biostar/m6tba broadcom/blast compaq/deskpro_en_sff_p600 digitallogic/adl8
Author: hailfinger Date: 2009-04-21 02:16:06 +0200 (Tue, 21 Apr 2009) New Revision: 4147
Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Config.lb trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb trunk/coreboot-v2/src/mainboard/asus/p2b-d/Config.lb trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb trunk/coreboot-v2/src/mainboard/axus/tc320/Config.lb trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb trunk/coreboot-v2/src/mainboard/bcom/winnet100/Config.lb trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Config.lb trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb trunk/coreboot-v2/src/mainboard/jetway/j7f24/Config.lb trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms6147/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb trunk/coreboot-v2/src/mainboard/olpc/btest/Config.lb trunk/coreboot-v2/src/mainboard/olpc/rev_a/Config.lb trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb trunk/coreboot-v2/src/mainboard/televideo/tc7020/Config.lb trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s1846/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb trunk/coreboot-v2/src/mainboard/via/epia/Config.lb trunk/coreboot-v2/src/mainboard/via/pc2500e/Config.lb trunk/coreboot-v2/src/mainboard/via/vt8454c/Config.lb Log: Thanks to Myles' patch adding support for include statements, refactoring Config.lb became possible.
Factor out ROM size calculation from Config.lb.
This patch converts 87 boards (with and without USE_FAILOVER_IMAGE), but it has to work around a parser bug.
89 files changed, 209 insertions(+), 2415 deletions(-) A total of 2206 removed lines.
Abuild works for all changed boards on khepri.
Myles writes: I've tested serengeti for the failover portion and s2892 for the nofailover portion. ldoptions are exactly the same and they both boot the same.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net Acked-by: Myles Watson mylesgw@gmail.com Acked-by: Peter Stuge peter@stuge.se Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,40 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## - -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -19,41 +19,8 @@ ## ##
+include /config/nofailovercalculation.lb
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,40 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## - -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -19,41 +19,8 @@ ## ##
+include /config/nofailovercalculation.lb
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,51 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /config/failovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -17,54 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA #
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /config/failovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -# -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -21,33 +21,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - default ROM_SECTION_OFFSET = 0 - end -end -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -# XIP_ROM_SIZE must be a power of 2. -# XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE. -default XIP_ROM_SIZE = 64 * 1024 -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end +include /config/failovercalculation.lb + arch i386 end driver mainboard.o # Needed by irq_tables and mptable and acpi_tables.
Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -20,21 +20,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb +default CONFIG_ROM_PAYLOAD = 1
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default CONFIG_ROM_PAYLOAD = 1 -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 65536 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) - arch i386 end
driver mainboard.o
Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-d/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end
Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end
Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/tc320/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/axus/tc320/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE object irq_tables.o end
Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,18 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -19,18 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE object irq_tables.o end
Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,37 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -21,54 +21,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /config/failovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /config/failovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,18 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,51 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /config/failovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -19,18 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE object irq_tables.o end
Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -20,43 +20,9 @@
## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## - -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) - - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -20,42 +20,9 @@
## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## - -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) - -## ## Set all of the defaults for an x86 architecture ## arch i386 end
Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/msi/ms6147/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,22 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) - -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) - -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) - arch i386 end driver mainboard.o
Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,18 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE object irq_tables.o end
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -22,53 +22,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - default ROM_SECTION_OFFSET = 0 - end -end +include /config/failovercalculation.lb
-## -## Compute the start location and size size of the coreboot bootloader. -## -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot ROM. -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte) -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE = (64 * 1024) - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,34 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - default ROM_SECTION_OFFSET = 0 - end -end +include /config/failovercalculation.lb
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end
driver mainboard.o
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -22,40 +22,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -22,41 +22,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb +default CONFIG_ROM_PAYLOAD = 1
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default CONFIG_ROM_PAYLOAD = 1 - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
Modified: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,18 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE object irq_tables.o end
Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /config/failovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/olpc/btest/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/btest/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/olpc/btest/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/olpc/rev_a/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/rev_a/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,41 +18,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,18 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 65536 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE object irq_tables.o end
Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb +default CONFIG_ROM_PAYLOAD = 1
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default CONFIG_ROM_PAYLOAD = 1 - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -16,54 +16,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /config/failovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /config/failovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -19,41 +19,8 @@ ## ##
+include /config/nofailovercalculation.lb
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,18 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,18 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 65536 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE object irq_tables.o end
Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,19 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE - + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb +default CONFIG_ROM_PAYLOAD = 1
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default CONFIG_ROM_PAYLOAD = 1 - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,37 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,37 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,37 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,37 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,37 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,37 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,41 +1,8 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1
-## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
- ## ## Build the objects we have code for in this directory. ##
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb +default CONFIG_ROM_PAYLOAD = 1
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default CONFIG_ROM_PAYLOAD = 1 - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,51 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /config/failovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /config/failovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /config/failovercalculation.lb
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end
##
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb +default CONFIG_ROM_PAYLOAD = 1
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default CONFIG_ROM_PAYLOAD = 1 - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb +default CONFIG_ROM_PAYLOAD = 1
-## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default CONFIG_ROM_PAYLOAD = 1 - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - arch i386 end
Modified: trunk/coreboot-v2/src/mainboard/via/epia/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/via/epia/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -19,18 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE object irq_tables.o end
Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
Modified: trunk/coreboot-v2/src/mainboard/via/pc2500e/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/pc2500e/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/via/pc2500e/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -18,18 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb + arch i386 end driver mainboard.o if HAVE_PIRQ_TABLE object irq_tables.o end
Modified: trunk/coreboot-v2/src/mainboard/via/vt8454c/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/vt8454c/Config.lb 2009-04-20 22:54:13 UTC (rev 4146) +++ trunk/coreboot-v2/src/mainboard/via/vt8454c/Config.lb 2009-04-21 00:16:06 UTC (rev 4147) @@ -19,41 +19,9 @@ ## MA 02110-1301 USA ##
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb
## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##
-
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