RE: Does anybody needs LinuxBIOS for VMware virtual machines?

If you haven't already tried... maybe a few out's to port 0x80 to slow things down.

Steve

-----Original Message-----
From: Richard Smith [mailto:[e-mail]] 
Sent: Tuesday, March 08, 2005 9:40 AM
To: Ronald G. Minnich
Cc: Dmitriy Budko; Eric W. Biederman; [e-mail]
Subject: Re: Does anybody needs LinuxBIOS for VMware virtual machines?
> As I found on some chipsets, the CPU can be too fast, and it should:
> start op
> wait for 'smbus active' indicator to go to 1
> wait for 'smbus active' indicator to go to 0
>
> is this by any chance your problem?

The code is basiclly a port of the working V1 assembly code converted
to C.  I seem to remember that the V1 code did exactly what you are
talking about.  Perhaps I goofed up a flag polarity or some other core
piece of info while doing it.

I'll whip up a patch today when I get to work and post it up for
anyone interested to look at.  Perhaps a fresh set of eyes will catch
the issue.

I'll need a place to upload to.  Or I guess you can commit to CVS.
Didn't someone mention that they were going to provide space for stuff
like this?

Does anybody needs LinuxBIOS for VMware virtual machines?

[Richard Smith]

On Tue, 8 Mar 2005 10:31:41 -0500, [e-mail]
 wrote:
> If you haven't already tried... maybe a few out's to port 0x80 to slow things down.

Thats a pretty quick and easy test.  I'll do that in a bit and see what happens.

Does anybody needs LinuxBIOS for VMware virtual machines?

[Richard Smith]

>  wrote:
> > If you haven't already tried... maybe a few out's to port 0x80 to slow things down.
>
> Thats a pretty quick and easy test.  I'll do that in a bit and see what happens.

No change.  I still get all 0xff's (not all zeros like I said earlier)

I think I'm a victim of my own cleverness.  Digging back into the code
I now rember that my port is _not_ just a port of the V1 assembly. 
Its a total rewrite.

My port is heavly based on the AMD solo board.  Thats the mainboard
that had a superIO closest to mine and out of all the boards I looked
at the AMD north and southbridge code was the cleanist and easiest to
follow.  So I basically took the smbus code from the amd8111 and
changed the register defines and bit flags to match the i440bx.

Well at least thats the theory.  Obviously I got something wrong.  The
structure for the sm_bus read already has a delay function in it.  It
was only one out(80,80) I bumped it up to 6 but no change.

I suspect that one of my flags is just incorrect.  What needs to
happen is lots of debug prints to watch the status register and verify
that a single read really does the right thing.

I was kinda hopeing it would just "work".  Sigh.

I can't really mess with it again till this weekend but if someone
else wants the code let me know.