New patch to review for coreboot: 2d3a5c5 Ivybridge: fix workaround and enable PAIR

[Stefan Reinauer]

Stefan Reinauer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1303

-gerrit

commit 2d3a5c5dc15508b84883af8071870e743653a562
Author: Duncan Laurie 
Date:   Sat Jun 23 20:14:07 2012 -0700

Ivybridge: fix workaround and enable PAIR

MCHBAR 0x5f10[7:0] should be set to 0x30 for ivybridge
    and 0x20 for sandybridge.  Move this code to ramstage
    and set it per-chipset.

Power Aware Interrupt Routing is supported in ivybridge,
    enable it and set fixed priority.

Boot on ivybridge device and read MCHBAR 0x5f10:

mmio_read8 0xfed15f10
    0x30

And verify PAIR is enabled (bit4=1):

mmio_read8 0xfed15418
    0x24

Change-Id: If017d5ce2bd5ab5092c86f657434f2b645ee6613
    Signed-off-by: Duncan Laurie 
---
 src/northbridge/intel/sandybridge/early_init.c  |    2 --
 src/northbridge/intel/sandybridge/northbridge.c |   19 +++++++++++++++++++
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 48faf5f..c7afa11 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -108,8 +108,6 @@ static void sandybridge_setup_graphics(void)
    pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8);

/* Erratum workarounds */
-	MCHBAR8(0x5f10) = 0x20;
-
    reg32 = MCHBAR32(0x5f00);
    reg32 |= (1 << 9)|(1 << 10);
    MCHBAR32(0x5f00) = reg32;
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 756aacf..2fa3504 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -387,9 +387,28 @@ static void northbridge_dmi_init(struct device *dev)
 static void northbridge_init(struct device *dev)
 {
    u8 bios_reset_cpl;
+	u32 bridge_type;

northbridge_dmi_init(dev);

+	bridge_type = MCHBAR32(0x5f10);
+	bridge_type &= ~0xff;
+
+	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+		/* Enable Power Aware Interrupt Routing */
+		u8 pair = MCHBAR8(0x5418);
+		pair &= ~0xf;	/* Clear 3:0 */
+		pair |= 0x4;	/* Fixed Priority */
+		MCHBAR8(0x5418) = pair;
+
+		/* 30h for IvyBridge */
+		bridge_type |= 0x30;
+	} else {
+		/* 20h for Sandybridge */
+		bridge_type |= 0x20;
+	}
+	MCHBAR32(0x5f10) = bridge_type;
+
    /*
     * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
     * that BIOS has initialized memory and power management