This is a repost, I'm hoping some folks missed it since the last time I posted it in a patch thread. I'm having problems getting the tyan s2507 to boot into linuxbios, it's hanging with a post code of 0x10, which according to POSTCODES is after it enters protected mode. I've used outb() to determine that it's hanging before it ever gets to the cpu or mainboard initialization, but I'm having trouble tracing it back any further, because the inner workings of LB have me very much lost.
I should probably mention that this is a dual p3 board, I don't know if cpu/intel/model_6xx was ever inteded to be used for SMP. I've tried this with and without smp, and even pulled one of the CPUs, and it still hangs. I've also tried with and without APIC, with no luck. I've attached my latest Config.lb and Options.lb from my s2507 folder. Please post back with any suggestions!
Thanks, Corey
-Corey
## ## Compute the location and size of where this firmware image ## (linuxBIOS plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) else default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) default ROM_SECTION_OFFSET = 0 end
## ## Compute the start location and size size of ## The linuxBIOS bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## ## Compute where this copy of linuxBIOS will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## ## Compute a range of ROM that can cached to speed up linuxBIOS, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE ## default XIP_ROM_SIZE=65536 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
## ## Set all of the defaults for an x86 architecture ##
arch i386 end
## ## Build the objects we have code for in this directory. ##
driver mainboard.o
#if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o
## ## Romcc output ## makerule ./failover.E depends "$(MAINBOARD)/failover.c ./romcc" action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" end
makerule ./failover.inc depends "$(MAINBOARD)/failover.c ./romcc" action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" end
makerule ./auto.E depends "$(MAINBOARD)/auto.c option_table.h ./romcc" action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end makerule ./auto.inc depends "$(MAINBOARD)/auto.c option_table.h ./romcc" action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end
## ## Build our 16 bit and 32 bit linuxBIOS entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds
## ## Build our reset vector (This is where linuxBIOS is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds end
### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc
## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds
### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end
### ### O.k. We aren't just an intermediary anymore! ###
## ## Setup RAM ## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/sse/enable_sse.inc mainboardinit ./auto.inc mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/mmx/disable_mmx.inc
## ## Include the secondary Configuration files ## dir /pc80 config chip.h
chip northbridge/via/vt694 device pci_domain 0 on end device apic_cluster 0 on chip cpu/intel/model_6xx device apic 0 on end end chip cpu/intel/model_6xx device apic 1 on end end end end
uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET uses HAVE_OPTION_TABLE uses USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD uses IRQ_SLOT_COUNT uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER uses LINUXBIOS_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE uses HEAP_SIZE uses ROM_SIZE uses ROM_SECTION_SIZE uses ROM_IMAGE_SIZE uses ROM_SECTION_SIZE uses ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses PAYLOAD_SIZE uses _ROMBASE uses _RAMBASE uses XIP_ROM_SIZE uses XIP_ROM_BASE uses HAVE_MP_TABLE uses CROSS_COMPILE uses CC uses HOSTCC uses OBJCOPY uses DEFAULT_CONSOLE_LOGLEVEL uses MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses TTYS0_BAUD uses TTYS0_BASE uses TTYS0_LCS uses CONFIG_UDELAY_TSC uses CONFIG_SMP uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses SERIAL_CPU_INIT uses FAKE_SPDROM
## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE = 256*1024
### ### Build options ###
default FAKE_SPDROM=1
## ## SMP and CPU stuffs ## default CONFIG_SMP=1 default CONFIG_MAX_CPUS=2 default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=0 default CONFIG_IOAPIC=1 default SERIAL_CPU_INIT=0
## ## Build code for the fallback boot ## default HAVE_FALLBACK_BOOT=1
## ## no MP table ## default HAVE_MP_TABLE=0
## ## Build code to reset the motherboard from linuxBIOS ## default HAVE_HARD_RESET=0
## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=0 default IRQ_SLOT_COUNT=4 #object irq_tables.o
## ## Build code to export a CMOS option table ## default HAVE_OPTION_TABLE=0
### ### LinuxBIOS layout values ###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. default ROM_IMAGE_SIZE = 65536 #default FALLBACK_SIZE = 131072 default FALLBACK_SIZE = 262144
## ## Use a small 8K stack ## default STACK_SIZE=0x2000
## ## Use a small 16K heap ## default HEAP_SIZE=0x4000
## ## Only use the option table in a normal image ## #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
## ## The default compiler ## default CROSS_COMPILE="" default CC="$(CROSS_COMPILE)gcc -m32 -fno-stack-protector" default HOSTCC="gcc -fno-stack-protector"
## ## The Serial Console ##
# To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate default TTYS0_BAUD=115200 #default TTYS0_BAUD=57600 #default TTYS0_BAUD=38400 #default TTYS0_BAUD=19200 #default TTYS0_BAUD=9600 #default TTYS0_BAUD=4800 #default TTYS0_BAUD=2400 #default TTYS0_BAUD=1200
# Select the serial console base port default TTYS0_BASE=0x3f8
# Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity default TTYS0_LCS=0x3
## ### Select the linuxBIOS loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately ## CRIT 3 critical conditions ## ERR 4 error conditions ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational ## DEBUG 8 debug-level messages ## SPEW 9 Way too many details
## Request this level of debugging output default DEFAULT_CONSOLE_LOGLEVEL=9 ## At a maximum only compile in this level of debugging default MAXIMUM_CONSOLE_LOGLEVEL=9
default CONFIG_UDELAY_TSC=1 end
Heh, fixed. I forgot to update failover.c when I built just the fallback image. I hate it when I find the solution 10 minutes after posting the problem, after having worked on it for 2 days prior to that...
-Corey
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Corey Osgood