Re: [LinuxBIOS] badly initialized (?) pci bridge on the M57SLI (with irq table and mptable)

Hi Ward,

I don't think that my little "quickie" deserves so much consideration, but I
will post it, hopping that it could be usefull for someone..
 Btw you have to do first a "setpci -s 00:01.1 64.l" to retrieve the base
address of the SYSCTRL register table. Use this value as a parameter for my
program to dump the io configuration (the gpio registers seem to start @ offset
0xc0 into this table..)
 Hope this helps,
  Florentin

Quoting Ward Vandewege :
> Hey Florentin,
>
> Fascinating!
>
> On Fri, Oct 05, 2007 at 03:00:15PM +0200, [e-mail] wrote:
> > Btw I figured out that registers of the "IO control unit" of mcp55
>
> can be
> > mapped into the IO space by writting into the SYSCTRL_REG of the 00:01.1
>
> pci
> > device integrated into the SB. Indeed by using this value as a base (under
> > Linux, this register holds the value 0x1400) one can access the GPIO
>
> registers
> > of MCP55 (beginning @ the 0xc0 offset? maybe..) These are 8 bit registers
> > apparently..
> > After booting with the proprietary Award bios, I dumped this table
>
> under
> > Linux (with a simple custom utility that I wrote for this purpose..). I
>
> dumped
> > 256 bytes from 0x1400.
>
> Would you mind sharing this utility with the list? It could be a very handy
> debugging tool.
>
> Thanks,
> Ward.

[LinuxBIOS] badly initialized (?) pci bridge on the M57SLI (with irq table and mptable)

[Peter Stuge]

On Mon, Oct 08, 2007 at 03:27:20AM +0200, [e-mail] wrote:
> for (i=0; i<0x100; i++) {
>     io_val = inb(io_addr);
>     printf(" %.8x : %.8x\n", io_addr, io_val);
>     io_addr++;
>   }

This can also be done with:

dd if=/dev/port bs=1 skip=0x1000 count=256|xxd -c1

but it does not print the actual port, only the offset.

//Peter

[LinuxBIOS] badly initialized (?) pci bridge on the M57SLI (with irq table and mptable)

[Ward Vandewege]

Hi Florentin,

On Mon, Oct 08, 2007 at 03:27:20AM +0200, [e-mail] wrote:
> I don't think that my little "quickie" deserves so much consideration, but I
> will post it, hopping that it could be usefull for someone..

Thank you!
> Btw you have to do first a "setpci -s 00:01.1 64.l" to retrieve the base
>  address of the SYSCTRL register table. Use this value as a parameter for
>  my program to dump the io configuration (the gpio registers seem to start
>  @ offset 0xc0 into this table..)

Yes, I've been able to verify all this. Your fix enables 1 of the 2 pci slots
(the one closest to the edge of the board is still broken).

There is something I don't understand, however.

When using io_dump under the proprietary BIOS, I see:

000014e5 : 00000068
 000014e6 : 00000068
 000014e7 : 00000068
 000014e8 : 00000048

When booted under LinuxBIOS (without your patch), I see this (the io
configuration starts at 0x2401 instead of 0x1401 under LB):

000024e5 : 00000004
 000024e6 : 00000004
 000024e7 : 00000004
 000024e8 : 00000004

The intriguing thing is that the LB code writes the following values to those
registers:

RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38
PCI_REQ3 */ \
        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39
PCI_GNT3 */ \
        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40
PCI_GNT2 */ \
        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41
PCI_REQ2 */ \

So why are those registers not all set to 0x44 as I would expect?

After applying your patch the code sets the registers to these values:

RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38
PCI_REQ3 */ \
        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39
PCI_GNT3 */ \
        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40
PCI_GNT2 */ \
        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41
PCI_REQ2 */ \

After booting into LB, we find:

000024e5 : 00000004
 000024e6 : 00000028
 000024e7 : 00000004
 000024e8 : 00000004

So the 68h has turned into 28h - but the PCI slot works!

Can you confirm what you see when you read out the values after booting in
LinuxBIOS, with your patch?

I've added debug code to src/northbridge/amd/amdk8/setup_resource_map.c to
make it be explicit about what it's doing.

0018: 22 000024e5 <- & 00000000 | 00000044
original value: 00000068
after &: 00000000
after |: 00000044
confirmed value: 00000044
0019: 22 000024e6 <- & 00000000 | 00000068
original value: 00000068
after &: 00000000
after |: 00000068
confirmed value: 00000028
001a: 22 000024e7 <- & 00000000 | 00000044
original value: 00000068
after &: 00000000
after |: 00000044
confirmed value: 00000044
001b: 22 000024e8 <- & 00000000 | 00000044
original value: 00000068
after &: 00000000
after |: 00000044
confirmed value: 00000044

So somehow 68h is turned into 28h when read back. It's as if there is a
sticky bit on that register.

And it looks like something is doing an & 10111111 sometime later during the
boot process turning 44h into 4h, but I have not figured out where that might
be happening.

Any thoughts?

Thanks,
Ward.

[LinuxBIOS] badly initialized (?) pci bridge on the M57SLI (with irq table and mptable)

Hi Ward,

Yes I confirm this behaviour, I observed it too (but omitted to mention it in
my previous posts..).
 Unfortunately I have no rational explanation for this. Btw it is extremely
difficult and time (and nerve!) consuming to work without at least a token
amount of technical documentation!..
 Please, please, if someone from NVidia is still reading this mailinglist, could
he/she answer for this very specific topic (the IO configuration for the PCI
signals of the MCP55 chip)? We are not asking for nothing else!..
 Thank you in advance!
  Florentin Demetrescu

Quoting Ward Vandewege :
> Hi Florentin,
>
> On Mon, Oct 08, 2007 at 03:27:20AM +0200, [e-mail] wrote:
> > I don't think that my little "quickie" deserves so much consideration, but
>
> I
> > will post it, hopping that it could be usefull for someone..
>
> Thank you!
> > Btw you have to do first a "setpci -s 00:01.1 64.l" to retrieve the base
> >  address of the SYSCTRL register table. Use this value as a parameter for
> >  my program to dump the io configuration (the gpio registers seem to start
> >  @ offset 0xc0 into this table..)
>
> Yes, I've been able to verify all this. Your fix enables 1 of the 2 pci slots
> (the one closest to the edge of the board is still broken).
>
> There is something I don't understand, however.
>
> When using io_dump under the proprietary BIOS, I see:
>
> 000014e5 : 00000068
>  000014e6 : 00000068
>  000014e7 : 00000068
>  000014e8 : 00000048
>
> When booted under LinuxBIOS (without your patch), I see this (the io
> configuration starts at 0x2401 instead of 0x1401 under LB):
>
> 000024e5 : 00000004
>  000024e6 : 00000004
>  000024e7 : 00000004
>  000024e8 : 00000004
>
> The intriguing thing is that the LB code writes the following values to those
> registers:
>     RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38
>
> PCI_REQ3 */ \
>         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39
> PCI_GNT3 */ \
>         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40
> PCI_GNT2 */ \
>         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41
> PCI_REQ2 */ \
>
> So why are those registers not all set to 0x44 as I would expect?
>
> After applying your patch the code sets the registers to these values:
>     RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38
>
> PCI_REQ3 */ \
>         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39
> PCI_GNT3 */ \
>         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40
> PCI_GNT2 */ \
>         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41
> PCI_REQ2 */ \
>
> After booting into LB, we find:
>
> 000024e5 : 00000004
>  000024e6 : 00000028
>  000024e7 : 00000004
>  000024e8 : 00000004
>
> So the 68h has turned into 28h - but the PCI slot works!
>
> Can you confirm what you see when you read out the values after booting in
> LinuxBIOS, with your patch?
>
> I've added debug code to src/northbridge/amd/amdk8/setup_resource_map.c to
> make it be explicit about what it's doing.
>
> 0018: 22 000024e5 <- & 00000000 | 00000044
> original value: 00000068
> after &: 00000000
> after |: 00000044
> confirmed value: 00000044
> 0019: 22 000024e6 <- & 00000000 | 00000068
> original value: 00000068
> after &: 00000000
> after |: 00000068
> confirmed value: 00000028
> 001a: 22 000024e7 <- & 00000000 | 00000044
> original value: 00000068
> after &: 00000000
> after |: 00000044
> confirmed value: 00000044
> 001b: 22 000024e8 <- & 00000000 | 00000044
> original value: 00000068
> after &: 00000000
> after |: 00000044
> confirmed value: 00000044
>
> So somehow 68h is turned into 28h when read back. It's as if there is a
> sticky bit on that register.
>
> And it looks like something is doing an & 10111111 sometime later during the
> boot process turning 44h into 4h, but I have not figured out where that might
> be happening.
>
> Any thoughts?
>
> Thanks,
> Ward.

[LinuxBIOS] badly initialized (?) pci bridge on the M57SLI (with irq table and mptable)

[Harald Gutmann]

i tried that patch today, but it doesn't help to geht pci-slots working on my 
board, which is a rev.2.0.

thus i don't really know which informations would be good to have from the pci 
things, i can't send them. but at the beginning i did an "lspci -xxxx -s 
00:06" on both bios versions.

from the propritary bios:
%<---------------------------------------------------------------------------------------------
00:06.0 PCI bridge: nVidia Corporation Unknown device 0370 (rev a2)
00: de 10 70 03 07 00 b0 00 a2 01 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 01 01 20 70 80 80 02
20: 00 fb f0 fc 10 fd 10 fd 00 00 00 00 00 00 00 00
30: 00 00 00 00 b8 00 00 00 00 00 00 00 00 00 00 0a
40: 00 00 33 07 01 00 02 00 05 00 00 00 00 00 44 00
50: 00 00 fe cf 00 00 00 00 eb 1f ff 1f 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 fe 2f 01 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 a8
90: 00 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00
a0: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 ff ff 00 00 0d 8c 00 00 00 00 00 00
c0: 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
%<-------------------------------------------------------------------------------------------

from the linuxbios with this patch patch:
%<-------------------------------------------------------------------------------------------
00:06.0 PCI bridge: nVidia Corporation Unknown device 0370 (rev a2)
00: de 10 70 03 04 01 b0 00 a2 00 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 f0 00 80 02
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 b8 00 00 00 00 00 00 00 00 00 03 0a
40: 00 00 33 07 01 00 02 00 05 00 00 00 00 00 4c 00
50: 00 00 00 e0 00 00 00 00 ff 1f ff 1f 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 a8
90: 00 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00
a0: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 ff ff 00 00 0d 8c 00 00 de 10 84 cb
c0: de 10 84 cb 07 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
%<--------------------------------------------------------------------------------------------

the second patch from yhlu has already been commited to the svn tree.

[LinuxBIOS] badly initialized (?) pci bridge on the M57SLI (with irq table and mptable)

[Harald Gutmann]

Am Montag, 15. Oktober 2007 21:56:47 schrieb Harald Gutmann:
> i tried that patch today, but it doesn't help to geht pci-slots working on
> my board, which is a rev.2.0.

seems that i've patched in the wrong directory (src not work).
the patch works for one slot.

i patched both lines, also the one for GPIO40:
 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \

at the first boot with my pci-soundcard and an 3com nic, in lspci both devices 
showed up, but the nic didn't work. (i'm sorry, but i don't have the log from 
dmesg any more. something with probe pci and -22 appeared there.

but after that all, it just works the first slot. my soundcard is also not 
recogniced in the second slot. (but both slots work with propritary bios.)

if some more output is required, please tell me!

regards, harald

[LinuxBIOS] badly initialized (?) pci bridge on the M57SLI (with irq table and mptable)

[Ward Vandewege]

Hi Harald,

On Tue, Oct 16, 2007 at 04:19:06PM +0200, Harald Gutmann wrote:
> Am Montag, 15. Oktober 2007 21:56:47 schrieb Harald Gutmann:
> > i tried that patch today, but it doesn't help to geht pci-slots working on
> > my board, which is a rev.2.0.
>
> seems that i've patched in the wrong directory (src not work).
> the patch works for one slot.

OK, thank you for that confirmation, that means that we now have 3 people
with 2 different revisions of the board that report that this patch fixes one
pci slot.

I suggest we add the patch to the main tree.

Florentin, do you want to make a patch with signed-off-by? I'll be happy to
ack and commit it.
> i patched both lines, also the one for GPIO40:
>  RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
>  RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
>
> at the first boot with my pci-soundcard and an 3com nic, in lspci both devices 
> showed up, but the nic didn't work. (i'm sorry, but i don't have the log from 
> dmesg any more. something with probe pci and -22 appeared there.
>
> but after that all, it just works the first slot. my soundcard is also not 
> recogniced in the second slot. (but both slots work with propritary bios.)

I tried that too, and got similar results - it does not fix the second pci
slot. I have a few other things I want to try based on the pci io dump, but I
have not had time yet. And there is the matter of the sticky bit that we have
not resolved...

Thanks,
Ward.

[LinuxBIOS] badly initialized (?) pci bridge on the M57SLI (with irq table and mptable)

[Uwe Hermann]

On Tue, Oct 16, 2007 at 10:30:02AM -0400, Ward Vandewege wrote:
> OK, thank you for that confirmation, that means that we now have 3 people
> with 2 different revisions of the board that report that this patch fixes one
> pci slot.
>
> I suggest we add the patch to the main tree.

Yep, as it only changes to m57sli code, I guess it's safe to apply.
> Florentin, do you want to make a patch with signed-off-by? I'll be happy to
> ack and commit it.

Please also add a small comment before the changed line which explains
the issue and how the value was found (maybe a link to the resp. post in the
list archives, too).

Uwe.