Please check the diff to fb2_mcp55_full_01172007.
More range for HT_CHAIN_UNITID_BASE and HT_CHAIN_END_UNITID_BASE. For example: in C51/MCP55 or C51/MCP51 Will allow 1. C51 at 0x10 to 0x14, and MCP at 0 to 4 2. C51 at 1 to 4, and MCP at 7 to 0x0a
The reason is c51/mcp51/mcp55 reported unitid is 0x0f (far beyond it needed), and will prevent us from putting them on bus 0.
Typical values for c51/mcp55 or c51/mcp51: HT_CHAIN_UNITID_BASE = 0x10 # for C51 HT_CHAIN_END_UNITID_BASE = 0 # for mcp
If only have mcp with c51, HT_CHAIN_UNITID_BASE = 0 # for MCP #HT_CHAIN_END_UNITID_BASE = 0 # default value 0x20
Signed-off-by: Yinghai Lu yinghai.lu@amd.com
-----Original Message----- From: linuxbios-bounces@linuxbios.org [mailto:linuxbios-bounces@linuxbios.org] On Behalf Of Lu, Yinghai Sent: Thursday, January 18, 2007 9:06 PM To: Ronald G Minnich; Eric W. Biederman Cc: linuxbios@linuxbios.org Subject: [LinuxBIOS] MCP55 LinuxBIOS with USB debug etc.
Please check the MCP55 support with usbdebug.
MB included: Nvidia l1_2pvv Gigabyte m57sli Supermicro h8dmr Tyan s2912 --- with HTX
Signed-off-by: Yinghai Lu yinghai.lu@amd.com
Lu, Yinghai wrote:
More range for HT_CHAIN_UNITID_BASE and HT_CHAIN_END_UNITID_BASE. For example: in C51/MCP55 or C51/MCP51 Will allow
- C51 at 0x10 to 0x14, and MCP at 0 to 4
- C51 at 1 to 4, and MCP at 7 to 0x0a
What? Why? How?
The reason is c51/mcp51/mcp55 reported unitid is 0x0f (far beyond it needed), and will prevent us from putting them on bus 0.
Is this a chipset bug?
Typical values for c51/mcp55 or c51/mcp51: HT_CHAIN_UNITID_BASE = 0x10 # for C51 HT_CHAIN_END_UNITID_BASE = 0 # for mcp
If only have mcp with c51, HT_CHAIN_UNITID_BASE = 0 # for MCP #HT_CHAIN_END_UNITID_BASE = 0 # default value 0x20
Can we get this properly documented in the code somewhere? The HT_CHAIN_ stuff is not exactly easy to understand.