This is probably just about done save for dram timing.
ron
On 28.02.2008 23:41, ron minnich wrote:
This is probably just about done save for dram timing.
ron
This set of changes adds what is probably mostly correct support for dbe62.
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
I like it. A few minor nitpicks, the rest is
Compile tested and Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Regards, Carl-Daniel
Index: mainboard/artecgroup/dbe62/Kconfig
--- mainboard/artecgroup/dbe62/Kconfig (revision 0) +++ mainboard/artecgroup/dbe62/Kconfig (revision 0) @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer stepan@coresystems.de for coresystems GmbH) +## Copyright (C) 2007 Ronald G. Minnich rminnich@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +##
+config MAINBOARD_NAME
- string
- default artecgroup/dbe62
- depends BOARD_ARTECGROUP_DBE62
- help
This is the default mainboard name.Index: mainboard/artecgroup/dbe62/stage1.c
--- mainboard/artecgroup/dbe62/stage1.c (revision 0) +++ mainboard/artecgroup/dbe62/stage1.c (revision 0) @@ -0,0 +1,69 @@ +/*
- This file is part of the coreboot project.
- Copyright (C) 2007 Advanced Micro Devices, Inc.
Add your copyright as well?
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
+#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <northbridge/amd/geodelx/raminit.h>
+static const struct wmsr {
- u32 reg;
- struct msr msr;
+}
Maybe split this and move the struct declaration to a header?
dbe62_msr[] = {
- {.reg = 0x10000020, {.lo = 0x00fff80, .hi = 0x20000000}},
- {.reg = 0x10000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
- {.reg = 0x40000020, {.lo = 0x00fff80, .hi = 0x20000000}},
- {.reg = 0x40000021, {.lo = 0x80fffe0, .hi = 0x20000000}},
+};
+static void dbe62_msr_init(void) +{
- int i;
- for (i = 0; i < ARRAY_SIZE(dbe62_msr); i++)
wrmsr(dbe62_msr[i].reg, dbe62_msr[i].msr);+}
+void hardware_stage1(void) +{
- post_code(POST_START_OF_MAIN);
- dbe62_msr_init();
- cs5536_stage1();
- /*
* NOTE: Must do this AFTER the early_setup! It is counting on some* early MSR setup for the CS5536.*/- cs5536_setup_onchipuart();
+}
+void mainboard_pre_payload(void) +{
- geode_pre_payload();
- banner(BIOS_DEBUG, "mainboard_pre_payload: done");
+} Index: mainboard/artecgroup/dbe62/irq_tables.c =================================================================== --- mainboard/artecgroup/dbe62/irq_tables.c (revision 0) +++ mainboard/artecgroup/dbe62/irq_tables.c (revision 0) @@ -0,0 +1,120 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2007 Advanced Micro Devices, Inc.
Add your copyright as well?
+* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/
+#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <pirq_routing.h> +#include <amd_geodelx.h> +#include "../../../southbridge/amd/cs5536/cs5536.h"
+/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 10 +#define PIRQD 11
+/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE,
- PIRQ_VERSION,
- 32 + 16 * 5, /* Max. number of devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
- 0x00, /* IRQs devoted exclusively to PCI usage */
- 0x100B, /* Vendor */
- 0x002B, /* Device */
- 0, /* Crap (miniport) */
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
- 0x00, /* Checksum */
- {
/* If you change the number of entries, change IRQ_SLOT_COUNT above! *//* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu *//* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
The comment above seems to exist twice.
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */{0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */- }
+};
+unsigned long write_pirq_routing_table(unsigned long addr) +{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- u16 chipset_irq_map;
- u32 pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
- pirtable_end = copy_pirq_routing_table(addr);
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
- pirq_tbl = (struct irq_routing_table *) (addr);
- num_entries = (pirq_tbl->size - 32) / 16;
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);for (j = 0; j < 4; j++) {printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,pirq_tbl->slots[i].irq[j].bitmap);/* Finds lsb in bitmap to IRQ#. */for (k = 0;(!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))&& (pirq_tbl->slots[i].irq[j].bitmap != 0);k++);pirq[j] = k;printk(BIOS_DEBUG, "PIRQ: %d\n", k);}/* Bus, device, slots IRQs for {A,B,C,D}. */pci_assign_irqs(pirq_tbl->slots[i].bus,pirq_tbl->slots[i].devfn >> 3, pirq);- }
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
+} Index: mainboard/artecgroup/dbe62/dts =================================================================== --- mainboard/artecgroup/dbe62/dts (revision 0) +++ mainboard/artecgroup/dbe62/dts (revision 0) @@ -0,0 +1,48 @@ +/*
- This file is part of the coreboot project.
- Copyright (C) 2007 Ronald G. Minnich rminnich@gmail.com
2008?
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
+/{
- mainboard-vendor = "Artec";
- mainboard-name = "DBE62";
- cpus { };
- apic@0 {
/config/("northbridge/amd/geodelx/apic");- };
- domain@0 {
/config/("northbridge/amd/geodelx/domain");pci@1,0 {/config/("northbridge/amd/geodelx/pci");};pci@15,0 {/config/("southbridge/amd/cs5536/dts");enable_ide = "1";/* Interrupt enables for LPC bus.* Each bit is an IRQ 0-15. */lpc_serirq_enable = "0x00001002";/* LPC IRQ polarity. Each bit is an IRQ 0-15. */lpc_serirq_polarity = "0x0000EFFD";/* 0:continuous 1:quiet */lpc_serirq_mode = "1";/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.* See virtual PIC spec. */enable_gpio_int_route = "0x0D0C0700";};- };
+}; Index: mainboard/artecgroup/dbe62/cmos.layout =================================================================== --- mainboard/artecgroup/dbe62/cmos.layout (revision 0) +++ mainboard/artecgroup/dbe62/cmos.layout (revision 0) @@ -0,0 +1,74 @@ +entries
+#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
+enumerations
+#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM
+checksums
+checksum 392 1007 1008
Index: mainboard/artecgroup/dbe62/Makefile
--- mainboard/artecgroup/dbe62/Makefile (revision 0) +++ mainboard/artecgroup/dbe62/Makefile (revision 0) @@ -0,0 +1,35 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006-2007 coresystems GmbH +## (Written by Stefan Reinauer stepan@coresystems.de for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +##
+STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
+INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \$(src)/arch/x86/geodelx/geodelx.c+STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_OBJ += irq_tables.o
Why set STAGE2_MAINBOARD_OBJ once and add to it once?
+$(obj)/coreboot.vpd:
- $(Q)printf " BUILD DUMMY VPD\n"
- $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
Index: mainboard/artecgroup/Kconfig
--- mainboard/artecgroup/Kconfig (revision 623) +++ mainboard/artecgroup/Kconfig (working copy) @@ -30,10 +30,23 @@ select OPTION_TABLE select NORTHBRIDGE_AMD_GEODELX select SOUTHBRIDGE_AMD_CS5536
- select PIRQ_TABLE help Artec Group DBE61, also known as ThinCan and Linutop.
+source "mainboard/artecgroup/dbe61/Kconfig"
Please move the line above to the end of the file. Otherwise you get strange artifacts in menuconfig after selecting dbe61.
+config BOARD_ARTECGROUP_DBE62
- bool "DBE62"
- select ARCH_X86
- select CPU_AMD_GEODELX
- select OPTION_TABLE
- select NORTHBRIDGE_AMD_GEODELX
- select SOUTHBRIDGE_AMD_CS5536
- select PIRQ_TABLE
- help
Artec Group DBE62, also known as ThinCan and Linutop.
AFAIK the Linutop 1 is equivalent to DBE61 and Linutop 2 is equivalent to DBE62.
endchoice
-source "mainboard/artecgroup/dbe61/Kconfig"
+source "mainboard/artecgroup/dbe62/Kconfig"
Committed revision 624.
There's only one nitpick I did not ack on. I put all your other changes in.
On Thu, Feb 28, 2008 at 3:07 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 28.02.2008 23:41, ron minnich wrote:
+static const struct wmsr {
u32 reg;struct msr msr;+}
Maybe split this and move the struct declaration to a header?
I've thought hard about this for a few years. I will let it be for now, it's such a simple thing and if moved to a .h it becomes one more 'grep for this' type struct.
thanks
ron
On 29.02.2008 00:14, ron minnich wrote:
Committed revision 624.
There's only one nitpick I did not ack on. I put all your other changes in.
Thanks.
On Thu, Feb 28, 2008 at 3:07 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 28.02.2008 23:41, ron minnich wrote:
+static const struct wmsr {
u32 reg;struct msr msr;+}
Maybe split this and move the struct declaration to a header
I've thought hard about this for a few years. I will let it be for now, it's such a simple thing and if moved to a .h it becomes one more 'grep for this' type struct.
The struct type already exists in include/arch/x86/msr.h: struct msrinit { u32 msrnum; struct msr msr; }; and it is used all over the place. It even has a nicely fitting name. Your choice.
Regards, Carl-Daniel
On Thu, Feb 28, 2008 at 3:26 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
The struct type already exists in include/arch/x86/msr.h: struct msrinit { u32 msrnum; struct msr msr; }; and it is used all over the place. It even has a nicely fitting name. Your choice.
attached and it builds.
ron
On 29.02.2008 00:35, ron minnich wrote:
On Thu, Feb 28, 2008 at 3:26 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
The struct type already exists in include/arch/x86/msr.h: struct msrinit { u32 msrnum; struct msr msr; }; and it is used all over the place. It even has a nicely fitting name. Your choice.
attached and it builds.
ron
Thanks!
Use an already-defined struct.
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Regards, Carl-Daniel
Committed revision 625.
On Thu, Feb 28, 2008 at 02:41:15PM -0800, ron minnich wrote:
+++ mainboard/artecgroup/dbe62/Kconfig (revision 0) +config MAINBOARD_NAME
- string
- default artecgroup/dbe62
- depends BOARD_ARTECGROUP_DBE62
- help
This is the default mainboard name.
What's a default name?
+void hardware_stage1(void) +{
- post_code(POST_START_OF_MAIN);
- dbe62_msr_init();
- cs5536_stage1();
- /*
* NOTE: Must do this AFTER the early_setup! It is counting on some* early MSR setup for the CS5536.*/- cs5536_setup_onchipuart();
+}
What early_setup?! Please fix this comment in all boards before it is copypasted again. I'll do it if someone tells me where this early MSR setup is done now. dbe62_msr_init() ?
+void mainboard_pre_payload(void) +{
- geode_pre_payload();
- banner(BIOS_DEBUG, "mainboard_pre_payload: done");
+}
Why do we need this mainboard code when it is only calling a function that can be determined using the dts?
+++ mainboard/artecgroup/dbe62/irq_tables.c (revision 0)
The final frontier.
+unsigned long write_pirq_routing_table(unsigned long addr)
What an abomination. hint hint ;)
Can this code really not live in northbridge/ ?
+/{
- mainboard-vendor = "Artec";
- mainboard-name = "DBE62";
..
/* LPC IRQ polarity. Each bit is an IRQ 0-15. */lpc_serirq_polarity = "0x0000EFFD";/* 0:continuous 1:quiet */lpc_serirq_mode = "1";/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.* See virtual PIC spec. */enable_gpio_int_route = "0x0D0C0700";
Yes! So completely on track. :)
//Peter
On Thu, Feb 28, 2008 at 5:00 PM, Peter Stuge peter@stuge.se wrote:
helpThis is the default mainboard name.What's a default name?
you'll have to ask the guy who wrote that Kconfig file. I'm just a humble intern.
/** NOTE: Must do this AFTER the early_setup! It is counting on some* early MSR setup for the CS5536.*/cs5536_setup_onchipuart();+}
What early_setup?! Please fix this comment in all boards before it is copypasted again. I'll do it if someone tells me where this early MSR setup is done now. dbe62_msr_init() ?
yes. Unlike just about any other board, due to the way this chipset works, the onchip uart is not independent in ways we are used to. Comment away!
+void mainboard_pre_payload(void) +{
geode_pre_payload();banner(BIOS_DEBUG, "mainboard_pre_payload: done");+}
Why do we need this mainboard code when it is only calling a function that can be determined using the dts?
Show me how. I don't know.
+unsigned long write_pirq_routing_table(unsigned long addr)
What an abomination. hint hint ;)
Can this code really not live in northbridge/ ?
no, it's a south function, with mainboard-dependent bits. I'm happy to see a way to make it generic, I just don't know how yet.
/* LPC IRQ polarity. Each bit is an IRQ 0-15. */lpc_serirq_polarity = "0x0000EFFD";/* 0:continuous 1:quiet */lpc_serirq_mode = "1";/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.* See virtual PIC spec. */enable_gpio_int_route = "0x0D0C0700";Yes! So completely on track. :)
are you happy or unhappy here? Just want to make sure ...
ron
On Thu, Feb 28, 2008 at 06:53:39PM -0800, ron minnich wrote:
On Thu, Feb 28, 2008 at 5:00 PM, Peter Stuge peter@stuge.se wrote:
helpThis is the default mainboard name.What's a default name?
you'll have to ask the guy who wrote that Kconfig file. I'm just a humble intern.
:) Change the help text to something better then.
+void mainboard_pre_payload(void) +{
geode_pre_payload();banner(BIOS_DEBUG, "mainboard_pre_payload: done");+}
Why do we need this mainboard code when it is only calling a function that can be determined using the dts?
Show me how. I don't know.
arch/x86/stage1.c currently calls mainboard_pre_payload() - for Geode LX the call has nothing to do with the mainboard and everything to do with the north.
geode_pre_payload() is defined in geodelx/geodelxinit.c, so one easy way is to rename it to northbridge_amd_geodelx_pre_payload() and generate the call from data in the dts.
Another way would be to add it to struct device_operations. I like that better actually.
+unsigned long write_pirq_routing_table(unsigned long addr)
What an abomination. hint hint ;)
Can this code really not live in northbridge/ ?
no, it's a south function, with mainboard-dependent bits. I'm happy to see a way to make it generic, I just don't know how yet.
Is the _code_ really mainboard dependent? I would think it's device dependent, and the board only changes input values. Am I off?
Yes! So completely on track. :)
are you happy or unhappy here? Just want to make sure ...
Very happy! I think v3 is really excellent save for a few things that I make much noise about.
//Peter
On 29.02.2008 14:41, Peter Stuge wrote:
On Thu, Feb 28, 2008 at 06:53:39PM -0800, ron minnich wrote:
On Thu, Feb 28, 2008 at 5:00 PM, Peter Stuge peter@stuge.se wrote:
helpThis is the default mainboard name.What's a default name?
you'll have to ask the guy who wrote that Kconfig file. I'm just a humble intern.
:) Change the help text to something better then.
"default name" is very misleading. Look at this snippet from the main Makefile: MAINBOARDDIR=$(shell echo $(CONFIG_MAINBOARD_NAME))
Maybe change the text to "This is the path of the directory for this mainboard below mainboard/ ." And once we have done that change, there is almost no reason not to rename that config variable to something else and/or use a better structure. I also believe this peculiarity is at fault for some of the weirdness I saw when rebuilding with a changed .config without make distclean in between.
+void mainboard_pre_payload(void) +{
geode_pre_payload();banner(BIOS_DEBUG, "mainboard_pre_payload: done");+}
Why do we need this mainboard code when it is only calling a function that can be determined using the dts?
Show me how. I don't know.
arch/x86/stage1.c currently calls mainboard_pre_payload() - for Geode LX the call has nothing to do with the mainboard and everything to do with the north.
geode_pre_payload() is defined in geodelx/geodelxinit.c, so one easy way is to rename it to northbridge_amd_geodelx_pre_payload() and generate the call from data in the dts.
Another way would be to add it to struct device_operations. I like that better actually.
Stage 2 phase 7?
+unsigned long write_pirq_routing_table(unsigned long addr)
What an abomination. hint hint ;)
Can this code really not live in northbridge/ ?
no, it's a south function, with mainboard-dependent bits. I'm happy to see a way to make it generic, I just don't know how yet.
Is the _code_ really mainboard dependent? I would think it's device dependent, and the board only changes input values. Am I off?
Once you use stuff like ARRAY_SIZE, it is difficult to make the code generic.
Regards, Carl-Daniel
On Fri, Feb 29, 2008 at 5:41 AM, Peter Stuge peter@stuge.se wrote:
+void mainboard_pre_payload(void) +{
geode_pre_payload();banner(BIOS_DEBUG, "mainboard_pre_payload: done");+}
Why do we need this mainboard code when it is only calling a function that can be determined using the dts?
Show me how. I don't know.
arch/x86/stage1.c currently calls mainboard_pre_payload() - for Geode LX the call has nothing to do with the mainboard and everything to do with the north.
geode_pre_payload() is defined in geodelx/geodelxinit.c, so one easy way is to rename it to northbridge_amd_geodelx_pre_payload() and generate the call from data in the dts.
Another way would be to add it to struct device_operations. I like that better actually.
Yep, but here you've hit a limitation in the design which we never thought of. Device stuff is in stage 2. But this mainboard_early stuff is in main (btw, we're going to need to rename arch/x86/stage1.c again -- since it calls stage2 and stage2 returns to it, it's not really a stage1 at all. I believe the name change was my mistake).
The device tree is in stage 2. It goes away at the end of stage2 since we didn't see a need for it. The data that it creates is gone at that point.
OK, it gets worse. You REALLY don't want to do this call until just about the last second, after payload is up and ready to go, since it disables ROM caching. That's a long time after stage 2. You can't do this call in stage2.
There are several options here but most of them are not that great. 1. add phase7 to stage 2 in device tree and return dynamic device tree from stage 2 to caller. stage2 phase 7 is now called AFTER payload is loaded and BEFORE payload is jumped to. This breaks our nice stage design but that's life. Big problem -- where does device tree go in memory and what do we do if it interferes with payload location? 2. what we have now -- it works. 3. name a pre-payload in the dts, have dtc build the mainboard_pre_payload function for us, call stays as it is now. 4. Linker sets -- Oh, yuck, a lot of work went into v3 to AVOID linker sets.
Let the comments begin!
+unsigned long write_pirq_routing_table(unsigned long addr)
What an abomination. hint hint ;)
Can this code really not live in northbridge/ ?
no, it's a south function, with mainboard-dependent bits. I'm happy to see a way to make it generic, I just don't know how yet.
Is the _code_ really mainboard dependent? I would think it's device dependent, and the board only changes input values. Am I off?
Sure, but it's almost always a southbridge thing. But you need to rewrite the code quite a bit to move it to the south directory, and I'm not sure it's worth it in the end -- having it in mainboard allows you to deal with mainboard bugs and problems very easily.
ron
On 29.02.2008 17:52, ron minnich wrote:
On Fri, Feb 29, 2008 at 5:41 AM, Peter Stuge peter@stuge.se wrote:
+void mainboard_pre_payload(void) +{
geode_pre_payload();banner(BIOS_DEBUG, "mainboard_pre_payload: done");+}
Why do we need this mainboard code when it is only calling a function that can be determined using the dts?
Show me how. I don't know.
arch/x86/stage1.c currently calls mainboard_pre_payload() - for Geode LX the call has nothing to do with the mainboard and everything to do with the north.
geode_pre_payload() is defined in geodelx/geodelxinit.c, so one easy way is to rename it to northbridge_amd_geodelx_pre_payload() and generate the call from data in the dts.
Another way would be to add it to struct device_operations. I like that better actually.
Yep, but here you've hit a limitation in the design which we never thought of. Device stuff is in stage 2. But this mainboard_early stuff is in main (btw, we're going to need to rename arch/x86/stage1.c again -- since it calls stage2 and stage2 returns to it, it's not really a stage1 at all. I believe the name change was my mistake).
Perhaps call it "launcher" stage? On the other hand, it is part of the bootblock (so either stage0 or stage1) and it is after CAR has been switched on (so definitely stage1). I vote to keep the name until we figure out something better.
The device tree is in stage 2. It goes away at the end of stage2 since we didn't see a need for it. The data that it creates is gone at that point.
OK, it gets worse. You REALLY don't want to do this call until just about the last second, after payload is up and ready to go, since it disables ROM caching. That's a long time after stage 2. You can't do this call in stage2.
There are several options here but most of them are not that great.
- add phase7 to stage 2 in device tree and return dynamic device tree
from stage 2 to caller. stage2 phase 7 is now called AFTER payload is loaded and BEFORE payload is jumped to. This breaks our nice stage design but that's life. Big problem -- where does device tree go in memory and what do we do if it interferes with payload location? 2. what we have now -- it works.
What we have now is OK, but there is room for improvement.
- name a pre-payload in the dts, have dtc build the
mainboard_pre_payload function for us, call stays as it is now. 4. Linker sets -- Oh, yuck, a lot of work went into v3 to AVOID linker sets.
5. Maybe the name of mainboard_pre_payload() is unfortunate and we should have pre_payload() which calls cpu_pre_payload(), chipset_pre_payload() and mainboard_pre_payload() in a row. That way, we don't have to put any GeodeLX ROM cache disabling below mainboard() and keep that stuff local to the southbridge code.
+unsigned long write_pirq_routing_table(unsigned long addr)
What an abomination. hint hint ;)
Can this code really not live in northbridge/ ?
no, it's a south function, with mainboard-dependent bits. I'm happy to see a way to make it generic, I just don't know how yet.
Is the _code_ really mainboard dependent? I would think it's device dependent, and the board only changes input values. Am I off?
Sure, but it's almost always a southbridge thing. But you need to rewrite the code quite a bit to move it to the south directory, and I'm not sure it's worth it in the end -- having it in mainboard allows you to deal with mainboard bugs and problems very easily.
Peter's idea was probably to separate code from data and I think there is some potential in that idea. write_pirq_routing_table() is identical for alix1c and dbe62 and could in theory really live in the south directory. AFAICS this wouldn't even require any changes in the function.
Regards, Carl-Daniel
On Fri, Feb 29, 2008 at 5:58 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
Peter's idea was probably to separate code from data and I think there is some potential in that idea. write_pirq_routing_table() is identical for alix1c and dbe62 and could in theory really live in the south directory. AFAICS this wouldn't even require any changes in the function.
it's a great idea. I just don't yet know how to do it.
ron
On 01.03.2008 03:03, ron minnich wrote:
On Fri, Feb 29, 2008 at 5:58 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
Peter's idea was probably to separate code from data and I think there is some potential in that idea. write_pirq_routing_table() is identical for alix1c and dbe62 and could in theory really live in the south directory. AFAICS this wouldn't even require any changes in the function.
it's a great idea. I just don't yet know how to do it.
Ron: The patch is also attached to reduce your gmail pain.
Factor out write_pirq_routing_table() for all GeodeLX targets. Compile tested on norwich, alix1c and dbe62. msm800sev is not affected and dbe61 is broken anyway.
svn is unable to create a valid patch for what I did, so I'll have to commit this myself. To reproduce, perform the following commands, then apply the patch:
svn mv mainboard/amd/norwich/irq_tables.c mainboard/amd/norwich/irq_tables.h svn mv mainboard/pcengines/alix1c/irq_tables.c mainboard/pcengines/alix1c/irq_tables.h svn mv mainboard/artecgroup/dbe61/irq_tables.c mainboard/artecgroup/dbe61/irq_tables.h svn mv mainboard/artecgroup/dbe62/irq_tables.c mainboard/artecgroup/dbe62/irq_tables.h
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c =================================================================== --- LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c (Revision 0) +++ LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c (Revision 0) @@ -0,0 +1,77 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2007 Advanced Micro Devices, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <pirq_routing.h> +#include <amd_geodelx.h> +#include <irq_tables.h> +#include "cs5536.h" + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + int i, j, k, num_entries; + unsigned char pirq[4]; + u16 chipset_irq_map; + u32 pciAddr, pirtable_end; + struct irq_routing_table *pirq_tbl; + + pirtable_end = copy_pirq_routing_table(addr); + + /* Set up chipset IRQ steering. */ + pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; + chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); + printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr, + chipset_irq_map); + outl(pciAddr & ~3, 0xCF8); + outl(chipset_irq_map, 0xCFC); + + pirq_tbl = (struct irq_routing_table *) (addr); + num_entries = (pirq_tbl->size - 32) / 16; + + /* Set PCI IRQs. */ + for (i = 0; i < num_entries; i++) { + printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i, + pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); + for (j = 0; j < 4; j++) { + printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j, + pirq_tbl->slots[i].irq[j].bitmap); + /* Finds lsb in bitmap to IRQ#. */ + for (k = 0; + (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) + && (pirq_tbl->slots[i].irq[j].bitmap != 0); + k++); + pirq[j] = k; + printk(BIOS_DEBUG, "PIRQ: %d\n", k); + } + + /* Bus, device, slots IRQs for {A,B,C,D}. */ + pci_assign_irqs(pirq_tbl->slots[i].bus, + pirq_tbl->slots[i].devfn >> 3, pirq); + } + + /* Put the PIR table in memory and checksum. */ + return pirtable_end; +} Index: LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile =================================================================== --- LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile (Arbeitskopie) @@ -23,6 +23,10 @@
STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
+ifeq ($(CONFIG_PIRQ_TABLE),y) +STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/irq_tables.o +endif + STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o
endif Index: LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h =================================================================== --- LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h (Arbeitskopie) @@ -93,49 +93,3 @@ {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */ } }; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - int i, j, k, num_entries; - unsigned char pirq[4]; - u16 chipset_irq_map; - u32 pciAddr, pirtable_end; - struct irq_routing_table *pirq_tbl; - - pirtable_end = copy_pirq_routing_table(addr); - - /* Set up chipset IRQ steering. */ - pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; - chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); - printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr, - chipset_irq_map); - outl(pciAddr & ~3, 0xCF8); - outl(chipset_irq_map, 0xCFC); - - pirq_tbl = (struct irq_routing_table *) (addr); - num_entries = (pirq_tbl->size - 32) / 16; - - /* Set PCI IRQs. */ - for (i = 0; i < num_entries; i++) { - printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i, - pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); - for (j = 0; j < 4; j++) { - printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j, - pirq_tbl->slots[i].irq[j].bitmap); - /* Finds lsb in bitmap to IRQ#. */ - for (k = 0; - (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) - && (pirq_tbl->slots[i].irq[j].bitmap != 0); - k++); - pirq[j] = k; - printk(BIOS_DEBUG, "PIRQ: %d\n", k); - } - - /* Bus, device, slots IRQs for {A,B,C,D}. */ - pci_assign_irqs(pirq_tbl->slots[i].bus, - pirq_tbl->slots[i].devfn >> 3, pirq); - } - - /* Put the PIR table in memory and checksum. */ - return pirtable_end; -} Index: LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile =================================================================== --- LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile (Arbeitskopie) @@ -26,7 +26,7 @@ $(src)/southbridge/amd/cs5536/smbus_initram.c \ $(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h =================================================================== --- LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h (Arbeitskopie) @@ -68,49 +68,3 @@ {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ } }; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - int i, j, k, num_entries; - unsigned char pirq[4]; - u16 chipset_irq_map; - u32 pciAddr, pirtable_end; - struct irq_routing_table *pirq_tbl; - - pirtable_end = copy_pirq_routing_table(addr); - - /* Set up chipset IRQ steering. */ - pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; - chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); - printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr, - chipset_irq_map); - outl(pciAddr & ~3, 0xCF8); - outl(chipset_irq_map, 0xCFC); - - pirq_tbl = (struct irq_routing_table *) (addr); - num_entries = (pirq_tbl->size - 32) / 16; - - /* Set PCI IRQs. */ - for (i = 0; i < num_entries; i++) { - printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i, - pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); - for (j = 0; j < 4; j++) { - printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j, - pirq_tbl->slots[i].irq[j].bitmap); - /* Finds lsb in bitmap to IRQ#. */ - for (k = 0; - (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) - && (pirq_tbl->slots[i].irq[j].bitmap != 0); - k++); - pirq[j] = k; - printk(BIOS_DEBUG, "PIRQ: %d\n", k); - } - - /* Bus, device, slots IRQs for {A,B,C,D}. */ - pci_assign_irqs(pirq_tbl->slots[i].bus, - pirq_tbl->slots[i].devfn >> 3, pirq); - } - - /* Put the PIR table in memory and checksum. */ - return pirtable_end; -} Index: LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile =================================================================== --- LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile (Arbeitskopie) @@ -25,7 +25,7 @@ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h =================================================================== --- LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h (Arbeitskopie) @@ -17,20 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <types.h> -#include <lib.h> -#include <console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <msr.h> -#include <io.h> #include <pirq_routing.h> -#include <amd_geodelx.h> -#include "../../../southbridge/amd/cs5536/cs5536.h"
- /* Platform IRQs */ #define PIRQA 11 #define PIRQB 10 @@ -112,49 +101,3 @@ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, } }; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - int i, j, k, num_entries; - unsigned char pirq[4]; - u16 chipset_irq_map; - u32 pciAddr, pirtable_end; - struct irq_routing_table *pirq_tbl; - - pirtable_end = copy_pirq_routing_table(addr); - - /* Set up chipset IRQ steering. */ - pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; - chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); - printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr, - chipset_irq_map); - outl(pciAddr & ~3, 0xCF8); - outl(chipset_irq_map, 0xCFC); - - pirq_tbl = (struct irq_routing_table *) (addr); - num_entries = (pirq_tbl->size - 32) / 16; - - /* Set PCI IRQs. */ - for (i = 0; i < num_entries; i++) { - printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i, - pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); - for (j = 0; j < 4; j++) { - printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j, - pirq_tbl->slots[i].irq[j].bitmap); - /* Finds lsb in bitmap to IRQ#. */ - for (k = 0; - (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) - && (pirq_tbl->slots[i].irq[j].bitmap != 0); - k++); - pirq[j] = k; - printk(BIOS_DEBUG, "PIRQ: %d\n", k); - } - - /* Bus, device, slots IRQs for {A,B,C,D}. */ - pci_assign_irqs(pirq_tbl->slots[i].bus, - pirq_tbl->slots[i].devfn >> 3, pirq); - } - - /* Put the PIR table in memory and checksum. */ - return pirtable_end; -} Index: LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile =================================================================== --- LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile (Arbeitskopie) @@ -25,7 +25,7 @@ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-pirq/Makefile =================================================================== --- LinuxBIOSv3-pirq/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/Makefile (Arbeitskopie) @@ -85,6 +85,7 @@ COREBOOTINCLUDE := -I$(src) -Iinclude \ -I$(src)/include \ -I$(src)/include/arch/$(ARCH)/ \ + -I$(src)/mainboard/$(MAINBOARDDIR)/ \ -include $(obj)/config.h \ -include $(obj)/build.h
You got it with code vs. data, Carl-Daniel. This is a nice good step towards what I meant! :)
I'll try to think a bit about how to express interrupt routing, but there is no point in a different syntax if it isn't more flexible. I think this will crystallize for k8.
On Sat, Mar 01, 2008 at 04:16:30PM +0100, Carl-Daniel Hailfinger wrote:
Ron: The patch is also attached to reduce your gmail pain.
Factor out write_pirq_routing_table() for all GeodeLX targets. Compile tested on norwich, alix1c and dbe62. msm800sev is not affected and dbe61 is broken anyway.
svn is unable to create a valid patch for what I did, so I'll have to commit this myself. To reproduce, perform the following commands, then apply the patch:
svn mv mainboard/amd/norwich/irq_tables.c mainboard/amd/norwich/irq_tables.h svn mv mainboard/pcengines/alix1c/irq_tables.c mainboard/pcengines/alix1c/irq_tables.h svn mv mainboard/artecgroup/dbe61/irq_tables.c mainboard/artecgroup/dbe61/irq_tables.h svn mv mainboard/artecgroup/dbe62/irq_tables.c mainboard/artecgroup/dbe62/irq_tables.h
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Acked-by: Peter Stuge peter@stuge.se
(but let's have some more comments)
Index: LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c
--- LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c (Revision 0) +++ LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c (Revision 0) @@ -0,0 +1,77 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2007 Advanced Micro Devices, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/
+#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <pirq_routing.h> +#include <amd_geodelx.h> +#include <irq_tables.h> +#include "cs5536.h"
+unsigned long write_pirq_routing_table(unsigned long addr) +{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- u16 chipset_irq_map;
- u32 pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
- pirtable_end = copy_pirq_routing_table(addr);
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
- pirq_tbl = (struct irq_routing_table *) (addr);
- num_entries = (pirq_tbl->size - 32) / 16;
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,pirq_tbl->slots[i].devfn,pirq_tbl->slots[i].slot);
for (j = 0; j < 4; j++) {printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,pirq_tbl->slots[i].irq[j].bitmap);/* Finds lsb in bitmap to IRQ#. */for (k = 0;(!((pirq_tbl->slots[i].irq[j].bitmap >> k) &1)) + && (pirq_tbl->slots[i].irq[j].bitmap != 0);
k++);pirq[j] = k;printk(BIOS_DEBUG, "PIRQ: %d\n", k);}/* Bus, device, slots IRQs for {A,B,C,D}. */pci_assign_irqs(pirq_tbl->slots[i].bus,pirq_tbl->slots[i].devfn >> 3, pirq);- }
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
+} Index: LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile =================================================================== --- LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile (Arbeitskopie) @@ -23,6 +23,10 @@
STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
+ifeq ($(CONFIG_PIRQ_TABLE),y) +STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/irq_tables.o +endif
STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o
endif Index: LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h =================================================================== --- LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h (Arbeitskopie) @@ -93,49 +93,3 @@ {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */ } };
-unsigned long write_pirq_routing_table(unsigned long addr) -{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- u16 chipset_irq_map;
- u32 pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
- pirtable_end = copy_pirq_routing_table(addr);
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
- pirq_tbl = (struct irq_routing_table *) (addr);
- num_entries = (pirq_tbl->size - 32) / 16;
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,pirq_tbl->slots[i].devfn,pirq_tbl->slots[i].slot);
for (j = 0; j < 4; j++) {printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,pirq_tbl->slots[i].irq[j].bitmap);/* Finds lsb in bitmap to IRQ#. */for (k = 0;(!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))&& (pirq_tbl->slots[i].irq[j].bitmap !=0);
k++);pirq[j] = k;printk(BIOS_DEBUG, "PIRQ: %d\n", k);}/* Bus, device, slots IRQs for {A,B,C,D}. */pci_assign_irqs(pirq_tbl->slots[i].bus,pirq_tbl->slots[i].devfn >> 3, pirq);- }
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
-} Index: LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile =================================================================== --- LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile (Arbeitskopie) @@ -26,7 +26,7 @@ $(src)/southbridge/amd/cs5536/smbus_initram.c \ $(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h =================================================================== --- LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h (Arbeitskopie) @@ -68,49 +68,3 @@ {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ } };
-unsigned long write_pirq_routing_table(unsigned long addr) -{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- u16 chipset_irq_map;
- u32 pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
- pirtable_end = copy_pirq_routing_table(addr);
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
- pirq_tbl = (struct irq_routing_table *) (addr);
- num_entries = (pirq_tbl->size - 32) / 16;
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,pirq_tbl->slots[i].devfn,pirq_tbl->slots[i].slot);
for (j = 0; j < 4; j++) {printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,pirq_tbl->slots[i].irq[j].bitmap);/* Finds lsb in bitmap to IRQ#. */for (k = 0;(!((pirq_tbl->slots[i].irq[j].bitmap >> k) &1)) - && (pirq_tbl->slots[i].irq[j].bitmap != 0);
k++);pirq[j] = k;printk(BIOS_DEBUG, "PIRQ: %d\n", k);}/* Bus, device, slots IRQs for {A,B,C,D}. */pci_assign_irqs(pirq_tbl->slots[i].bus,pirq_tbl->slots[i].devfn >> 3, pirq);- }
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
-} Index: LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile =================================================================== --- LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile (Arbeitskopie) @@ -25,7 +25,7 @@ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h =================================================================== --- LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h (Arbeitskopie) @@ -17,20 +17,9 @@
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <types.h> -#include <lib.h> -#include <console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <msr.h> -#include <io.h> #include <pirq_routing.h> -#include <amd_geodelx.h> -#include "../../../southbridge/amd/cs5536/cs5536.h"
/* Platform IRQs */ #define PIRQA 11 #define PIRQB 10 @@ -112,49 +101,3 @@ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, } };
-unsigned long write_pirq_routing_table(unsigned long addr) -{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- u16 chipset_irq_map;
- u32 pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
- pirtable_end = copy_pirq_routing_table(addr);
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
- pirq_tbl = (struct irq_routing_table *) (addr);
- num_entries = (pirq_tbl->size - 32) / 16;
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,pirq_tbl->slots[i].devfn,pirq_tbl->slots[i].slot);
for (j = 0; j < 4; j++) {printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,pirq_tbl->slots[i].irq[j].bitmap);/* Finds lsb in bitmap to IRQ#. */for (k = 0;(!((pirq_tbl->slots[i].irq[j].bitmap >> k) &1)) - && (pirq_tbl->slots[i].irq[j].bitmap != 0);
k++);pirq[j] = k;printk(BIOS_DEBUG, "PIRQ: %d\n", k);}/* Bus, device, slots IRQs for {A,B,C,D}. */pci_assign_irqs(pirq_tbl->slots[i].bus,pirq_tbl->slots[i].devfn >> 3, pirq);- }
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
-} Index: LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile =================================================================== --- LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile (Arbeitskopie) @@ -25,7 +25,7 @@ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-pirq/Makefile =================================================================== --- LinuxBIOSv3-pirq/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/Makefile (Arbeitskopie) @@ -85,6 +85,7 @@ COREBOOTINCLUDE := -I$(src) -Iinclude \ -I$(src)/include \ -I$(src)/include/arch/$(ARCH)/ \
-I$(src)/mainboard/$(MAINBOARDDIR)/ \ -include $(obj)/config.h \ -include $(obj)/build.h
Index: LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c
--- LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c (Revision 0) +++ LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c (Revision 0) @@ -0,0 +1,77 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2007 Advanced Micro Devices, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/
+#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <pirq_routing.h> +#include <amd_geodelx.h> +#include <irq_tables.h> +#include "cs5536.h"
+unsigned long write_pirq_routing_table(unsigned long addr) +{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- u16 chipset_irq_map;
- u32 pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
- pirtable_end = copy_pirq_routing_table(addr);
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
- pirq_tbl = (struct irq_routing_table *) (addr);
- num_entries = (pirq_tbl->size - 32) / 16;
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);for (j = 0; j < 4; j++) {printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,pirq_tbl->slots[i].irq[j].bitmap);/* Finds lsb in bitmap to IRQ#. */for (k = 0;(!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))&& (pirq_tbl->slots[i].irq[j].bitmap != 0);k++);pirq[j] = k;printk(BIOS_DEBUG, "PIRQ: %d\n", k);}/* Bus, device, slots IRQs for {A,B,C,D}. */pci_assign_irqs(pirq_tbl->slots[i].bus,pirq_tbl->slots[i].devfn >> 3, pirq);- }
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
+} Index: LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile =================================================================== --- LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile (Arbeitskopie) @@ -23,6 +23,10 @@
STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
+ifeq ($(CONFIG_PIRQ_TABLE),y) +STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/irq_tables.o +endif
STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o
endif Index: LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h =================================================================== --- LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h (Arbeitskopie) @@ -93,49 +93,3 @@ {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */ } };
-unsigned long write_pirq_routing_table(unsigned long addr) -{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- u16 chipset_irq_map;
- u32 pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
- pirtable_end = copy_pirq_routing_table(addr);
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
- pirq_tbl = (struct irq_routing_table *) (addr);
- num_entries = (pirq_tbl->size - 32) / 16;
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);for (j = 0; j < 4; j++) {printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,pirq_tbl->slots[i].irq[j].bitmap);/* Finds lsb in bitmap to IRQ#. */for (k = 0;(!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))&& (pirq_tbl->slots[i].irq[j].bitmap != 0);k++);pirq[j] = k;printk(BIOS_DEBUG, "PIRQ: %d\n", k);}/* Bus, device, slots IRQs for {A,B,C,D}. */pci_assign_irqs(pirq_tbl->slots[i].bus,pirq_tbl->slots[i].devfn >> 3, pirq);- }
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
-} Index: LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile =================================================================== --- LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile (Arbeitskopie) @@ -26,7 +26,7 @@ $(src)/southbridge/amd/cs5536/smbus_initram.c \ $(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h =================================================================== --- LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h (Arbeitskopie) @@ -68,49 +68,3 @@ {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ } };
-unsigned long write_pirq_routing_table(unsigned long addr) -{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- u16 chipset_irq_map;
- u32 pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
- pirtable_end = copy_pirq_routing_table(addr);
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
- pirq_tbl = (struct irq_routing_table *) (addr);
- num_entries = (pirq_tbl->size - 32) / 16;
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);for (j = 0; j < 4; j++) {printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,pirq_tbl->slots[i].irq[j].bitmap);/* Finds lsb in bitmap to IRQ#. */for (k = 0;(!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))&& (pirq_tbl->slots[i].irq[j].bitmap != 0);k++);pirq[j] = k;printk(BIOS_DEBUG, "PIRQ: %d\n", k);}/* Bus, device, slots IRQs for {A,B,C,D}. */pci_assign_irqs(pirq_tbl->slots[i].bus,pirq_tbl->slots[i].devfn >> 3, pirq);- }
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
-} Index: LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile =================================================================== --- LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile (Arbeitskopie) @@ -25,7 +25,7 @@ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h =================================================================== --- LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h (Arbeitskopie) @@ -17,20 +17,9 @@
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <types.h> -#include <lib.h> -#include <console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <msr.h> -#include <io.h> #include <pirq_routing.h> -#include <amd_geodelx.h> -#include "../../../southbridge/amd/cs5536/cs5536.h"
/* Platform IRQs */ #define PIRQA 11 #define PIRQB 10 @@ -112,49 +101,3 @@ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, } };
-unsigned long write_pirq_routing_table(unsigned long addr) -{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- u16 chipset_irq_map;
- u32 pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
- pirtable_end = copy_pirq_routing_table(addr);
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
- pirq_tbl = (struct irq_routing_table *) (addr);
- num_entries = (pirq_tbl->size - 32) / 16;
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);for (j = 0; j < 4; j++) {printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,pirq_tbl->slots[i].irq[j].bitmap);/* Finds lsb in bitmap to IRQ#. */for (k = 0;(!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))&& (pirq_tbl->slots[i].irq[j].bitmap != 0);k++);pirq[j] = k;printk(BIOS_DEBUG, "PIRQ: %d\n", k);}/* Bus, device, slots IRQs for {A,B,C,D}. */pci_assign_irqs(pirq_tbl->slots[i].bus,pirq_tbl->slots[i].devfn >> 3, pirq);- }
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
-} Index: LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile =================================================================== --- LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile (Arbeitskopie) @@ -25,7 +25,7 @@ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_OBJ =
$(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-pirq/Makefile =================================================================== --- LinuxBIOSv3-pirq/Makefile (Revision 626) +++ LinuxBIOSv3-pirq/Makefile (Arbeitskopie) @@ -85,6 +85,7 @@ COREBOOTINCLUDE := -I$(src) -Iinclude \ -I$(src)/include \ -I$(src)/include/arch/$(ARCH)/ \
-I$(src)/mainboard/$(MAINBOARDDIR)/ \ -include $(obj)/config.h \ -include $(obj)/build.h
It looks great but don't commit until I or someone else tests on hardware.
thanks
ron
Tested on alix1c. Ethernet, USB, graphics, serial all work.
Committed revision 628.
On 01.03.2008 22:34, ron minnich wrote:
Tested on alix1c. Ethernet, USB, graphics, serial all work.
Committed revision 628.
Thanks. And fixed in revision 629. (There was a reason why I wrote that I have to commit it myself...)
Regards, Carl-Daniel
Carl-Daniel,
Just tried the new irq table code on Norwich. Everything seems to be working. Thanks for making these changes. This is much cleaner.
Marc
Marc,
thanks for testing! Does that mean the Norwich works without any problems and we can change the v3 status of Norwich to OK here: http://www.coreboot.org/Supported_Motherboards
Regards, Carl-Daniel
Carl-Daniel,
Yes, Norwich works fine. I don't know of any issues. Go ahead and change the status in the wiki.
Marc
Marc,
thanks for verifying. Norwich v3 status in the wiki has been changed to "OK".
Are you working on a db800 port for v3? If not, I'd like to give it a first try.
Regards, Carl-Daniel
Carl-Daniel,
That was my plan but some family10 stuff has come up. I think it would be great if you want to do that port. Looking farther in the mail-list, I see that you have a patch. I will test it this morning.
Marc
Carl-Daniel Hailfinger wrote:
Marc,
thanks for verifying. Norwich v3 status in the wiki has been changed to "OK".
Are you working on a db800 port for v3? If not, I'd like to give it a first try.
Regards, Carl-Daniel
On Fri, Feb 29, 2008 at 5:58 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
- Maybe the name of mainboard_pre_payload() is unfortunate and we
should have pre_payload() which calls cpu_pre_payload(), chipset_pre_payload() and mainboard_pre_payload() in a row. That way, we don't have to put any GeodeLX ROM cache disabling below mainboard() and keep that stuff local to the southbridge code.
My concern here is we're going to walk our way back to the v1 style functions that end up mostly empty (e.g. mainboard_pre_payload(){}) on most targets. Mainboard_pre_payload is a hack but I have no good ideas on workarounds. Let's think this out some more. We'll get it.
The chipsets are always changing our ideas on how to set up the software :-)
ron
On 01.03.2008 03:06, ron minnich wrote:
On Fri, Feb 29, 2008 at 5:58 PM, Carl-Daniel Hailfinger wrote:
- Maybe the name of mainboard_pre_payload() is unfortunate and we
should have pre_payload() which calls cpu_pre_payload(), chipset_pre_payload() and mainboard_pre_payload() in a row. That way, we don't have to put any GeodeLX ROM cache disabling below mainboard() and keep that stuff local to the southbridge code
My concern here is we're going to walk our way back to the v1 style functions that end up mostly empty (e.g. mainboard_pre_payload(){}) on most targets. Mainboard_pre_payload is a hack but I have no good ideas on workarounds. Let's think this out some more. We'll get it.
Actually, these empty functions should be zero cost in the binary with gcc, but they clutter the source code. Hmm. I'd like something like "overridable functions" similar to weak functions, but where gcc is able to strip out the call if no non-empty function exists.
The chipsets are always changing our ideas on how to set up the software :-)
Indeed.
Regards, Carl-Daniel
-
Carl-Daniel Hailfinger -
Marc Jones -
Peter Stuge -
ron minnich