Hi all !!
This is my first post to the mailing list and my first question too :). First of all I want to say that I am pleased to talk to everyone around here.
Well, the problem is called M57SLI-S4 and its socketed bios. A problem, not a problem, who knows.
I am thinking on flashing the bios without desoldering it, one mistake and ... bye bye. Maybe I will have access to a desoldering station, but I have no experience with plcc chips, and maybe the person who works with it would have the same as I.
Has anyone found anything about the "second" plcc socket?
One friend of mine had a very "no no no, it don't likes me" idea, he says that one way of removing the plcc bios could be cutting the chip pins, but despite the "very intrusive" way, I will lose the chip, its information, I must to buy at least another chip (I am looking for it), and worst, I must to reprogram it (If I damage the current bios for putting a socket, the system will get bricked without bios, and I will not have the swap option ...).
Despite this, I wish to know one thing, it is common to get the board bricked?, I say that because if someone can help me verifying the steps, parameters, and so on, I think that I will try the "Russian Roulette" with this board. In this case what information I must give to you (some charitable soul ;) )
Well thats all, thanks, and best regards from Spain.
On 27/03/07, Beth beth.null@gmail.com wrote:
if someone can help me verifying the steps, parameters, and so on, I think that I will try the "Russian Roulette" with this board. In this case what information I must give to you (some charitable soul ;) )
Yes, I'm also waiting to play the Russian game :-)
Hi Dave, :) :)
To the end of the weekend I will finish the hardware setup for this board, memory and processor, please keep in touch, because as soon as I finish I will try it (if I don't found any option).
So ... :)
Regards.
On 3/27/07, Dave Crossland dave@lab6.com wrote:
On 27/03/07, Beth beth.null@gmail.com wrote:
if someone can help me verifying the steps, parameters, and so on, I think that I will try the "Russian Roulette" with this board. In this case what information I must give to you (some charitable soul ;) )
Yes, I'm also waiting to play the Russian game :-)
-- Regards, Dave
-- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
On Tue, Mar 27, 2007 at 04:24:36PM +0100, Dave Crossland wrote:
On 27/03/07, Beth beth.null@gmail.com wrote:
if someone can help me verifying the steps, parameters, and so on, I think that I will try the "Russian Roulette" with this board. In this case what information I must give to you (some charitable soul ;) )
Yes, I'm also waiting to play the Russian game :-)
I've put a howto online here:
http://linuxbios.org/M57SLI-S4_Build_Tutorial
The idea of cutting off the chip seems like a really bad one. Desoldering with a heat gun, and putting a socket on, is possible - a friend did it for my board.
The m57sli code in the v2 tree is not entirely complete yet, but that will hopefully change in a couple of days.
Thanks, Ward.
Yes I think that is the most aggressive one, and maybe a bit of investigation on the second plcc socket will be funny.
Your HowTo is very helpful for me, and I had read it a few times, but first of all I need to save my ass (jiji) finding the way of socketing the bios, so my efforts will be in this direction, If I couldn't have access to the desoldering station I will try it without "life-guard".
So as I am writting to ST, I will put a bit of time to the second socket.
Thanks and best regards.
On 3/27/07, Ward Vandewege ward@gnu.org wrote:
On Tue, Mar 27, 2007 at 04:24:36PM +0100, Dave Crossland wrote:
On 27/03/07, Beth beth.null@gmail.com wrote:
if someone can help me verifying the steps, parameters, and so on, I think that I will try the "Russian Roulette" with this board. In this case what information I must give to you (some charitable soul ;) )
Yes, I'm also waiting to play the Russian game :-)
I've put a howto online here:
http://linuxbios.org/M57SLI-S4_Build_Tutorial
The idea of cutting off the chip seems like a really bad one. Desoldering with a heat gun, and putting a socket on, is possible - a friend did it for my board.
The m57sli code in the v2 tree is not entirely complete yet, but that will hopefully change in a couple of days.
Thanks, Ward.
-- Ward Vandewege ward@fsf.org Free Software Foundation - Senior System Administrator
-- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Hi,
I hope other people will answer you, just my 10 cents:
I bought chip from http://bios-repair.co.uk/
4.21 Pounds only including postage ;)
(I have socked bios)
Rudolf
On 27/03/07, Rudolf Marek r.marek@assembler.cz wrote:
(I have socked bios)
That's the problem - These boards are not socketed :-(
Thanks Rudolf, I am seeking for a local dealer, but If I don't found any I will try outside Spain.
Regards, Jose.
On 3/27/07, Rudolf Marek r.marek@assembler.cz wrote:
Hi,
I hope other people will answer you, just my 10 cents:
I bought chip from http://bios-repair.co.uk/
4.21 Pounds only including postage ;)
(I have socked bios)
Rudolf
On 27/03/07, Rudolf Marek r.marek@assembler.cz wrote:
I bought chip from http://bios-repair.co.uk/
I just spoke to the nice chap who runs that site, and he is willing to desolder the existing BIOS chip and put a BIOS Saviour on the board, for around £20. He says he can't guarantee the work, and he thinks the pads may become weak through the process so extra must be taken when moving chips, but that he's happy to do it.
Thanks for mentioning this resource, Rudolf!
On Tue, Mar 27, 2007 at 05:35:32PM +0200, Rudolf Marek wrote:
Hi,
I hope other people will answer you, just my 10 cents:
I bought chip from http://bios-repair.co.uk/
4.21 Pounds only including postage ;)
(I have socked bios)
Wait -- you mean you have a socketed GA-M57SLI-S4? Or did you mean you have _some_ mainboard with socketed chip?
Uwe.
[Please always write to the mailing list, not individual developers]
----- Forwarded message from Beth beth.null@gmail.com -----
From: Beth beth.null@gmail.com To: Uwe Hermann uwe@hermann-uwe.de Subject: Re: [LinuxBIOS] New with a GA-M57SLI-S4 Date: Wed, 28 Mar 2007 10:45:26 +0200
Ooops, sorry I want to say a soldered one, I will have no problems with a socketed bios, sorry for the mistake.
Regards, Jose.
On 3/27/07, Uwe Hermann uwe@hermann-uwe.de wrote:
On Tue, Mar 27, 2007 at 05:35:32PM +0200, Rudolf Marek wrote:
Hi,
I hope other people will answer you, just my 10 cents:
I bought chip from http://bios-repair.co.uk/
4.21 Pounds only including postage ;)
(I have socked bios)
Wait -- you mean you have a socketed GA-M57SLI-S4? Or did you mean you have _some_ mainboard with socketed chip?
Uwe.
http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux)
iD8DBQFGCVbuXdVoV3jWIbQRAkcJAJ9ZLaddi+y+JDzn7WhxOHu+Vve8jgCgiMvZ CND/l2w3rKrXUGMQUxI26Cs= =HxtJ -----END PGP SIGNATURE-----
-- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Hi
Has anyone found anything about the "second" plcc socket?
I was planning to investigate this. But currently i am a little short on free time. So if you are patient or if you have some multimeter you can check if the pins from bios chip are connected to the equivalent free contacts.
I have taken already an look at the dualbios stuff from gigabyte. It seems as both bios chips should contain the same bios (at least partly) and some software logic determines which chip it activates for booting. Well it's patented so there "should" be some information available but so far i haven't found the corresponding patent filings (are they public or only available with the ever involved "bling" when it comes these patents ?).
Then there has to be some logic which decides to boot from which chip. But if s.o. can dig up the filings we probably know more?
Then it would be nice if someone from the list could point out which flash chips might be compatible with the free contacts. Also there has been some remarks on this list that the inner contacts may be some kind of rom contacts and the outer are flash contacts.
So before bricking your mainboard just try to dig up the above information? And probably we will find a way to enable an dual boot between the original bios and the linuxbios, which would be quite neat.
ST
Hi ST, nice to talk to you.
Today I don't have time, I must go to work now, but as soon as I can I will try to make the pin to pin test.
If they are directly connected it's true that maybe a software switch make the selection of which bios take the control at start up, I am not a low level man (a bit a bit), but without specifications and as you say with the patents on hand will be hard to find how it is done. Maybe dis assembling the code, but as I say, my low level knowledge is very low :D.
As soon as I can i will put my hands on the multimeter or the oscilloscope and do something (the bricking is not on my plans, yet :D).
Regards, Jose.
On 3/27/07, ST st@iss.tu-darmstadt.de wrote:
Hi
Has anyone found anything about the "second" plcc socket?
I was planning to investigate this. But currently i am a little short on free time. So if you are patient or if you have some multimeter you can check if the pins from bios chip are connected to the equivalent free contacts.
I have taken already an look at the dualbios stuff from gigabyte. It seems as both bios chips should contain the same bios (at least partly) and some software logic determines which chip it activates for booting. Well it's patented so there "should" be some information available but so far i haven't found the corresponding patent filings (are they public or only available with the ever involved "bling" when it comes these patents ?).
Then there has to be some logic which decides to boot from which chip. But if s.o. can dig up the filings we probably know more?
Then it would be nice if someone from the list could point out which flash chips might be compatible with the free contacts. Also there has been some remarks on this list that the inner contacts may be some kind of rom contacts and the outer are flash contacts.
So before bricking your mainboard just try to dig up the above information? And probably we will find a way to enable an dual boot between the original bios and the linuxbios, which would be quite neat.
ST
-- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Hi Jose
Well, one of my harddisk started acting strange so i had to open my case...
Well the result in pretty raw format right now. Bios Chip is a: PMC 0621 Pm49FLOO4T-33JCE If someone can enlighten me or has pointers to a datasheet, that would be nice.
I counted the pins the totally wrong way by starting clockwise at the flattened corner of the chip. It has 32 Pins. The open Solder Pins where counted in the same way.
Bios Pins connected to back 1 1,2 2 2,1 3 3 4 ? 5 5 6 6 7 7,WP_BIOS_2,T13
top 8 8 9 9,WP_BIOS_2,T13 10 ? 11 ? 12 12,WP_BIOS_2,T13 13 Interesting see Note below! 14 14,BT_PCI_2 15 ? 16 ? front 17 ? 18 ? 19 19,WP_BIOS_2,T13 20 20 21 21,WP_BIOS_2,T13 22 22 23 23 bottom 24 24 25 ? 26 ? 27 ? 28 ? 29 29 30 30,WP_BIOS_1 31 31,WP_BIOS_2,T13 32 32,WP_BIOS_2,T13
WP_BIOS Pins are very probably not soldered three headed jumper pin where "white" marked pin is 1 (the one torwards the back). I think it means "Write Protect".
T1 and T2 are two connectors (of a total of four) that consist of three solder points right in front of the PCIe*1 link connectors. The last number is the pin number also counted from the back.
I found that T22 is connected to the bios pin 13 and T12 is connected to the unsoldered pin 13. This is the only difference if found in the connection of the bios and unsoldered pins. I think pin 13 is the CE (Chip Enable) of this bios chip?
T13,T23 and WP_BIOS_2 are connected.
So Jose if you like you can try to figure out where these question marks are connected to.
If they are directly connected it's true that maybe a software switch make the selection of which bios take the control at start up, I am not a low level man (a bit a bit), but without specifications and as you say with the patents on hand will be hard to find how it is done.
I think the flash bios is connected to the multi io chip? Is this ITE labled chip an super io chip?
Maybe dis assembling the code, but as I say, my low level knowledge is very low :D.
Disassembling is a pain in the ... . I think if we can find out the connections between these chips we are better of.
As soon as I can i will put my hands on the multimeter or the oscilloscope and do something (the bricking is not on my plans, yet
Fine. I think the best way forward right now is to find the Datasheets, reorder the pin count and match the functions to my list above. After we have some knowledge about the involved chips, you can probably remeasure and verify our guesses?
I have taken already an look at the dualbios stuff from gigabyte. It seems as both bios chips should contain the same bios (at least partly) and some software logic determines which chip it activates for booting. Well it's patented so there "should" be some information available but so far i haven't found the corresponding patent filings (are they public or only available with the ever involved "bling" when it comes these patents ?).
So nobody has an idea how to obtain this stuff. This patent stuff is very awkward.
Then there has to be some logic which decides to boot from which chip.
If the bios failure should be detected this only works reliably with an watchdog which switches the bios on failure.
ST
* ST st@iss.tu-darmstadt.de [070328 00:36]:
Well the result in pretty raw format right now. Bios Chip is a: PMC 0621 Pm49FLOO4T-33JCE If someone can enlighten me or has pointers to a datasheet, that would be nice.
http://www.chingistek.com/resource_center/docs/Pm49FL002-004%20V1.8.pdf
If the bios failure should be detected this only works reliably with an watchdog which switches the bios on failure.
Many of them fake and do a software process. Doesn't hurt as long as the first chip always stays intact. But it's kind of useless for linuxbios.
Am Mittwoch, 28. März 2007 01:15 schrieb Stefan Reinauer:
- ST st@iss.tu-darmstadt.de [070328 00:36]:
Well the result in pretty raw format right now. Bios Chip is a: PMC 0621 Pm49FLOO4T-33JCE If someone can enlighten me or has pointers to a datasheet, that would be nice.
http://www.chingistek.com/resource_center/docs/Pm49FL002-004%20V1.8.pdf
Thanks :-) So the pin 13 in my totally wrong counting mode is OE or Init. So the pins for switching between the two flash chips should be known.
Many of them fake and do a software process. Doesn't hurt as long as the first chip always stays intact. But it's kind of useless for linuxbios.
I think gigabyte uses both, they have a virtual dual bios and a dual bios? But the information on their website is very thin.
ST
Just found this. Gigabyte's DualBios patent: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=...
I'm fairly sure I could have shortened the url, but if you don't like it, just don't use it ;)
-Corey
Corey Osgood wrote:
Just found this. Gigabyte's DualBios patent: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=...
I'm fairly sure I could have shortened the url, but if you don't like it, just don't use it ;)
-Corey
Sorry, I'm not sure if that's the right one or not. Here's a list of Giga-byte's patents:
http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=...
-Corey
Hi Cory
Just found this. Gigabyte's DualBios patent: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=... 2Fnetahtml%2Fsearch-adv.htm&r=8&f=G&l=50&d=PALL&S1=6651188.UREF.&OS=ref/66 51188&RS=REF/6651188
Thanks for digging this up. This patent is a joke: "Certain variations would be apparent to those skilled in the art, which variations are considered within the spirit and scope of the claimed invention.". Yeah great.
The description is very vague and not very helpful. I think the only thing it shows is that this patent system is a job security program for lawyers but not helpful in the advance of the mankind.
The only interesting thing i found is that they seem to use a checksum or s.t. to test if the bios image is valid.
ST
On Wed, Mar 28, 2007 at 05:28:55AM -0400, Corey Osgood wrote:
Sorry, I'm not sure if that's the right one or not. Here's a list of Giga-byte's patents:
This is it:
http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=...
The patent images even have a schematic for the timer/switcher circuit.
The two components in the patent schematic are either T1/T2 (Q2/Q43, or is it Q2/U20?) or Q4/Q5 on the board. I'm guessing more around Q2/Q43(U20?) but the easiest way would be if someone could draw up a simple schematic for the pads on their board.
//Peter
On Wed, Mar 28, 2007 at 05:21:11AM -0400, Corey Osgood wrote:
Just found this. Gigabyte's DualBios patent: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=...
I interpret this to be regarding embedding VGA and SCSI BIOS software (interface BIOS) backups within the system BIOS, for when an option ROM causes a system to not start properly.
//Peter
On Wed, Mar 28, 2007 at 12:36:19AM +0200, ST wrote:
I counted the pins the totally wrong way by starting clockwise at the flattened corner of the chip. It has 32 Pins. The open Solder Pins where counted in the same way.
Chip pin = (37-yourpin) mod 32
I looked up the relevant pins in the data sheet:
Bios Pins connected to 3 3
2, RST#
5 5
32, Vcc
6 6
31, CLK
12 12,WP_BIOS_2,T13
25, Vcc, this does not make sense.
Vcc is the power to the chip. WP_BIOS_2 is GND. That would mean there is a short circuit. Could you try switching the probes around to rule out that there is a protection diode somewhere allowing current one way but not the other?
13 Interesting see Note below!
24, INIT#, a second reset
14 14,BT_PCI_2
23, LFRAME#
20 20
17, LAD3
21 21,WP_BIOS_2,T13
16, GND
22 22
15, LAD2
23 23
14, LAD1
24 24
13, LAD0
The board may already support real dual BIOS in hardware!
Seeing how the chips are wired, there may already be logic on board to first try one chip then the other. It all depends on INIT#.
29 29 30 30,WP_BIOS_1
8, TBL# and 7, WP#
TBL is top boot block protection. WP is write protection for the entire chip except the top boot block. The protection is active if the pins are connected to GND. You found that GND was also WP_BIOS_2. This means that the chip would be write protected if there was a jumper shorting WP_BIOS_1 and WP_BIOS_2 together, which supports your theory! :)
I found that T22 is connected to the bios pin 13 and T12 is connected to the unsoldered pin 13. This is the only difference if found in the connection of the bios and unsoldered pins. I think pin 13 is the CE (Chip Enable) of this bios chip?
Pin 24 INIT# is probably used as a kind of chip enable signal, just backwards; when INIT# is pulled low, the chip will be in reset and act as if it wasn't there.
It would be interesting to know what signal is present on (empty) pad 24 during boot, specifically if the signal ever goes high. You could try to set the scope to trigger on a rising edge and see if the scope triggers during a boot. Don't slip with the probe! :)
Also, what are T22 and T12?
Could you check if either of them is connected to any pin on the superio? (But I doubt it.)
T13,T23 and WP_BIOS_2 are connected.
GND again.
So Jose if you like you can try to figure out where these question marks are connected to.
All pins/pads you marked with ? are either N/C (not connected) or RES (reserverd) on the chip and can be ignored for booting purposes.
If they are directly connected it's true that maybe a software
[..]
I think the flash bios is connected to the multi io chip? Is this ITE labled chip an super io chip?
The IT8716F is a super IO, yes.
//Peter
Hi Peter, Stefan, Corey, Jose
Chip pin = (37-yourpin) mod 32
Unfortunately i counted clockwise while the std pin numeration is counter-clockwise. This makes the pinsfunctions somehow weird and your work unfortunately moot... but you managed to motivate me to take a closer look :-).
Bios Pins connected to True Pin(tm) back 1 1,2 4 A8,GPI2 2 2,1 3 A9,GPI3 3 3 2 RST# 4 ? 1 NC 5 5 32 VCC 6 6 31 R/C# CLK 7 7,WP_BIOS_2,T13 30 A10,GPI4
top 8 8 29 IC 9 9,WP_BIOS_2,T13 28 NC <-Error? 10 ? 27 NC 11 ? 26 NC 12 12,WP_BIOS_2,T13 25 VCC <- Error? 13 24 OE#,Init# <- nice 14 14,BT_PCI_2 23 WE#,LFrame,FWH4 15 ? 22 NC 16 ? 21 I/O7 front 17 ? 20 I/O6 18 ? 19 I/O5 19 19,WP_BIOS_2,T13 18 I/O4 <-Error? 20 20 17 I/O3,LAD3,FWH3 21 21,WP_BIOS_2,T13 16 GND <-error? 22 22 15 I/O2,LAD2,FWH2 23 23 14 I/O1,LAD1,FWH1 bottom 24 24 13 I/O0,LAD0,FWH0 25 ? 12 A0,RES,ID0 26 ? 11 A1,RES,ID1 27 ? 10 A2,RES,ID2 28 ? 9 A3,RES,ID3 29 29 8 A4,TBL#,TBL# 30 30,WP_BIOS_1 7 A5,WP# <-makes sense 31 31,WP_BIOS_2,T13 6 A6,GPI0,GPI0 32 32,WP_BIOS_2,T13 5 A7,GPI1,GPI1
So according to my great connection list VCC is connected to GND. Ouch, who has designed this MB 8-). Oh wait... Jose could you do me a favor and recheck these lines with error? (Btw. our listing of the not connected pins is identical to mine). Especially the T1 or T2 pin and WP_BIOS connections.
TBL is top boot block protection.
This doesn't seem to connect to any of the jumpers.
WP is write protection for the entire chip except the top boot block.... which supports your theory! :)
Jup.
Also, what are T22 and T12?
Please see: http://private.vlsi.informatik.tu-darmstadt.de/st/dual_bios_GA-m57SLI-S4.jpg
These are open pins which might be transistors but are only Three open pins each. Between the PCIex1 sockets and the flash chips.
T13,T23 and WP_BIOS_2 are connected.
Theres some error in there. I'm not sure. But WP# is active low so, at least WP_BIOS_2 should be GND or s.t. like that?
All pins/pads you marked with ? are either N/C (not connected) or RES (reserverd) on the chip and can be ignored for booting purposes.
Yeah, i think there is not to much doubt. The only thing (beside my obvious error i made somewhere with the VCC pin). The fact that ID0-ID3 are not connected pins seems to lie in the fact that these are the identification inputs for the chips. This makes multiple FWH Chips possible. WE,LFRAME,FWH4 is connected to the jumper PCI_BT. Could that mean s.t. like PCI boot or is this also write protection? It would be nice if this jumper could control WE for each chip somehow, but i doubt it.
Pins I/O4-I/O6 seem to be unused. Which means that the chip is not used in A/A Mux mode. Thus the A6-A9 pins or better the GPIO0-GPI4 pins are also not used. I think they are all pulled to ground. Which leaves us with no unknown pins for both sockets?
Open questions: * How can writing to only one chip be realized? * Are these lower open pads above Q4 and R102 really not connected? Somehow i think these should be the transistors for controlling the write pins of these chips.
Good night ST
PS: I haven't taken a closer look at the patent.
Hi,
On Thu, Mar 29, 2007 at 12:23:12AM +0200, ST wrote:
Hi Peter, Stefan, Corey, Jose
Chip pin = (37-yourpin) mod 32
Unfortunately i counted clockwise while the std pin numeration is counter-clockwise. This makes the pinsfunctions somehow weird and your work unfortunately moot...
I hate to be a besserwisser, but I did take into account you numbering the pins clockwise. The simple formula should be correct except for pin 32, when it returns 0. :p
but you managed to motivate me to take a closer look :-).
Excellent! The more eyes the better.
Bios Pins connected to True Pin(tm)
[..]
A comment on the pin names. This chip supports three usage modes; A/A Mux, LPC and FWH.
A/A Mux is used for factory programming of unconnected flash chips. It's a parallell mode allowing fast flashing.
LPC is Low Pin Count, which is what is used on this board.
FWH is Firmware Hub, which is just like LPC but with a few extras, most notably the ID0-ID3 signals which would distinguish several chips otherwise connected in parallell.
So according to my great connection list VCC is connected to GND. Ouch, who has designed this MB 8-). Oh wait... Jose could you do me a favor and recheck these lines with error?
WP_BIOS_2 is definately GND considering the kind of input WP_BIOS_1 is connected to and the other places that connect to WP_BIOS_2.
The only confusion comes from pin 25 which should be Vcc, but the connection to GND could (and surely does) have an explanation.
(Btw. our listing of the not connected pins is identical to mine). Especially the T1 or T2 pin and WP_BIOS connections.
TBL is top boot block protection.
This doesn't seem to connect to any of the jumpers.
No.
Also, what are T22 and T12?
Please see: http://private.vlsi.informatik.tu-darmstadt.de/st/dual_bios_GA-m57SLI-S4.jpg
Thanks! Good picture.
BIOS_WP is write protection.
Shorting 1-2 on PCI_BT would pull LFRAME low on both chips, effectively disabling them, supporting the suggestion that booting from the PCI bus would be allowed. (But more hardware has to be involved to make it happen, possibly included in the chipset, possibly componentes not populated on the final boards.)
These are open pins which might be transistors but are only Three open pins each. Between the PCIex1 sockets and the flash chips.
They could be transistors or diodes. Hard to tell..
But it's nice to have some pads to solder on! :)
T13,T23 and WP_BIOS_2 are connected.
Theres some error in there. I'm not sure. But WP# is active low so, at least WP_BIOS_2 should be GND or s.t. like that?
Sure. T1-3 and T2-3 are GND. The wider traces also support that suggestion.
All pins/pads you marked with ? are either N/C (not connected) or RES (reserverd) on the chip and can be ignored for booting purposes.
[..]
I think they are all pulled to ground. Which leaves us with no unknown pins for both sockets?
None of them are relevant for LPC.
Open questions:
- How can writing to only one chip be realized?
Not just writing, but using. If we learn how pin 24 INIT# is controlled on both of the chips we may be able to create a simple BIOS savior circuit on the mainboard itself.
INIT# is the only relevant signal that isn't connected straight across.
- Are these lower open pads above Q4 and R102 really not connected?
Somehow i think these should be the transistors for controlling the write pins of these chips.
I'm not sure.
It seems Q4-2 is connected to pin 2 RST# - could you verify that?
I would guess Q4-3 is connected to GND.
Is the left pad of R89 in the picture (the one nearest T2 with a wide trace that runs into the Q4 outline) connected to Vcc or GND?
Use e.g. chip pin 32 for Vcc.
//Peter
Happy Easter
I just had some time to take a look at the pin connections i posted under the same subject a while ago.
Looking at the jumpers it looks like the flash program itself can control which of the (physically partly non-existant) flash chips is to be programmed. Pin 13 of the PM49FL004 is #Init. Init has to be high while while accessing the chip (in both Modes LPC and FWH). So i am pretty sure that flashbios is may be the only needed key to make this work. It would be nice if anybody could give me an pointer where this Mainboard specific stuff is located in flashbios (i have only glanced over the sources) and if someone knows which pin is connected to the soldered flash chip.
I would like to buy another flash chip. But all local dealers don't have any flash chips at hand :-(. Do i need the PM49FL004 or will any other PLCC32 flash chip do? Any pointers for german buyers?
Thanks ST
Hi,
On Sun, Apr 08, 2007 at 12:13:52AM +0200, ST wrote:
Looking at the jumpers it looks like the flash program itself can control which of the (physically partly non-existant) flash chips is to be programmed. Pin 13 of the PM49FL004 is #Init. Init has to be high while while accessing the chip (in both Modes LPC and FWH). So i am pretty sure that flashbios is may be the only needed key to make this work. It would be nice if anybody could give me an pointer where this Mainboard specific stuff is located in flashbios (i have only glanced over the sources)
You mean flashrom (not flashbios)?
It has been recently moved to board_enable.c, see http://tracker.linuxbios.org/trac/LinuxBIOS/browser/trunk/LinuxBIOSv2/util/f...
and if someone knows which pin is connected to the soldered flash chip.
No idea, sorry.
I would like to buy another flash chip. But all local dealers don't have any flash chips at hand :-(. Do i need the PM49FL004 or will any other PLCC32 flash chip do? Any pointers for german buyers?
Most electronics dealers should have some, e.g. Conrad: http://www.conrad.de.
Or try one of these: - http://bios-chip.de/ - http://www.bios-fix.de
eBay has lots of them, too (but not too cheap, usually).
HTH, Uwe.
happy Easter dudes !
at ebay Germany you find some guys who offer BIOS (searchword BIOS) replacement chips ready burned. if they do not have yout plcc type, they may get it somewhere. please keep us informed. --Q from Bremen
ST schrieb:
I would like to buy another flash chip. But all local dealers don't have any flash chips at hand :-(. Do i need the PM49FL004 or will any other PLCC32 flash chip do? Any pointers for german buyers?
-
Beth -
Corey Osgood -
Dave Crossland -
Peter Stuge -
Quux -
Rudolf Marek -
ST -
Stefan Reinauer -
Uwe Hermann -
Ward Vandewege