These patches reduce the boot time for me on my epia-cn. (From payload launch in 2.273s down to 0.610s.) Where possible, I tried to make the changes apply to other boards. However, I have not tested any other boards.
Kevin O'Connor (4): Make initializing PS2 keyboard optional. Enable TSC calibration with timer2 by default. Reduce TSC calibrations from 20ms to 2ms. Don't preload the rom code during the VIA CAR setup.
src/Kconfig | 14 ++++++++++++++ src/cpu/via/car/cache_as_ram.inc | 2 ++ src/cpu/x86/Kconfig | 2 +- src/cpu/x86/tsc/delay_tsc.c | 4 ++-- src/pc80/keyboard.c | 2 ++ 5 files changed, 21 insertions(+), 3 deletions(-)
Add a DRIVERS_PS2_KEYBOARD option which controls the PS2 keyboard initialization. Not all payloads require it and some keyboards take a long time to init.
Signed-off-by: Kevin O'Connor kevin@koconnor.net --- src/Kconfig | 14 ++++++++++++++ src/pc80/keyboard.c | 2 ++ 2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig index ec3a13b..ebbb14a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -120,6 +120,20 @@ endmenu
menu "Generic Drivers" source src/drivers/Kconfig + +config DRIVERS_PS2_KEYBOARD + bool "PS2 Keyboard init" + default y + help + Enable this option to initialize PS2 keyboards found connected + to the PS2 port. Some payloads (eg, filo) require this + option. Other payloads (eg, SeaBIOS, Linux) do not require + it. Initializing a PS2 keyboard can take several hundred + milliseconds. + + If you know you will only use a payload which does not require + this option, then you can say "n" here to speed up boot time. + Otherwise say "y". endmenu
config PCI_BUS_SEGN_BITS diff --git a/src/pc80/keyboard.c b/src/pc80/keyboard.c index dee6279..9dadf0e 100644 --- a/src/pc80/keyboard.c +++ b/src/pc80/keyboard.c @@ -162,6 +162,8 @@ static u8 send_keyboard(u8 command) void pc_keyboard_init(struct pc_keyboard *keyboard) { u8 regval; + if (!CONFIG_DRIVERS_PS2_KEYBOARD) + return; printk(BIOS_DEBUG, "Keyboard init...\n");
/* Run a keyboard controller self-test */
Enable TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 by default. Without this set, almost all boards use the inb(0x80) method. Unfortunately, that method takes over a second to calibrate, and it's results are not as reliable.
There is a chance that some boards may not work well with the timer2 method. This is likely rare, because both libpayload and seabios use the timer2 method unconditionally and there has not been reports of an issue. Should a board not support the more accurate timer2 mechanism, it will need to be updated to actively disable it.
Signed-off-by: Kevin O'Connor kevin@koconnor.net --- src/cpu/x86/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 325991e..8cd999e 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -21,7 +21,7 @@ config UDELAY_TSC
config TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 bool - default n + default y
config XIP_ROM_BASE hex
2ms is enough time to accurately obtain the clock rate.
Signed-off-by: Kevin O'Connor kevin@koconnor.net --- src/cpu/x86/tsc/delay_tsc.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 27c89e3..1127867 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -18,8 +18,8 @@ static unsigned long clocks_per_usec; * device. */
-#define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */ -#define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */ +#define CALIBRATE_INTERVAL ((2*CLOCK_TICK_RATE)/1000) /* 2ms */ +#define CALIBRATE_DIVISOR (2*1000) /* 2ms / 2000 == 1usec */
static unsigned long long calibrate_tsc(void) {
It should not be necessary to read in the rom during CAR setup. Removing the code preloading reduces the boot time.
Signed-off-by: Kevin O'Connor kevin@koconnor.net --- src/cpu/via/car/cache_as_ram.inc | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index eaa4ac9..4bbefef 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -139,10 +139,12 @@ clear_fixed_var_mtrr_out: xorl $0x5c5c5c5c,%eax rep stosl
+#ifdef CARTEST movl REAL_XIP_ROM_BASE, %esi movl %esi, %edi movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx rep lodsl +#endif
/* The key point of this CAR code is C7 cache does not turn into * "no fill" mode, which is not compatible with general CAR code.
-
Kevin O'Connor