[LinuxBIOS] Is the Cache as Ram for Gx2 processor?

[Hao Li]

Hello all,

Is there cache as ram codes for amd gx2 processor?

I don not think the codes in cpu/amd/car will work fine with gx2.

[Stefan Reinauer]

* Hao Li  [070406 15:06]:
> Hello all,
>
> Is there cache as ram codes for amd gx2 processor?
>
> I don not think the codes in cpu/amd/car will work fine with gx2…

Why?

[Tom Sylla]

Stefan Reinauer wrote:
> Hao Li  [070406 15:06]:
> > Hello all,
> >
> > Is there cache as ram codes for amd gx2 processor?
> >
> > I don not think the codes in cpu/amd/car will work fine with gx2…
>
> Why?

Because AMD GX and LX share little with the AMD64 architecture. From 
looking at the CAR code, it does a lot of its work with MTRRs. Geodes do 
not have MTRRs, so it just won't work as-is. (they have similar 
functionality to MTRRs, but they are not compatible)

As Hao is suspecting, AMD64 CAR won't work on Geode.

There isn't anything in LB to do CAR (but it would be possible).

[Stefan Reinauer]

* Tom Sylla  [070406 15:50]:
> Because AMD GX and LX share little with the AMD64 architecture. From 
> looking at the CAR code, it does a lot of its work with MTRRs. Geodes do 
> not have MTRRs, so it just won't work as-is. (they have similar 
> functionality to MTRRs, but they are not compatible)
>
> As Hao is suspecting, AMD64 CAR won't work on Geode.
>
> There isn't anything in LB to do CAR (but it would be possible).

As LinuxBIOS v3 wont support any systems which dont have CAR working, 
how can we find out what is required to get CAR working on Geode CPUs?

Stefan

[LinuxBIOS] 答复: Is the Cache as Ram for Gx2 processor?

[Hao Li]

Maybe we can look through Gx2's databook to find out. :)
Gx2 has mtrr-like registers which can be used for CAR I think...not so sure.

-----邮件原件-----
发件人: Stefan Reinauer [mailto:[e-mail]] 
发送时间: 2007年4月6日 21:56
收件人: Tom Sylla
抄送: Hao Li; [e-mail]
主题: Re: [LinuxBIOS] Is the Cache as Ram for Gx2 processor?

* Tom Sylla  [070406 15:50]:
> Because AMD GX and LX share little with the AMD64 architecture. From 
> looking at the CAR code, it does a lot of its work with MTRRs. Geodes do 
> not have MTRRs, so it just won't work as-is. (they have similar 
> functionality to MTRRs, but they are not compatible)
>
> As Hao is suspecting, AMD64 CAR won't work on Geode.
>
> There isn't anything in LB to do CAR (but it would be possible).

As LinuxBIOS v3 wont support any systems which dont have CAR working, 
how can we find out what is required to get CAR working on Geode CPUs?

Stefan

[ron minnich]

On 4/6/07, Stefan Reinauer  wrote:
> As LinuxBIOS v3 wont support any systems which dont have CAR working,
> how can we find out what is required to get CAR working on Geode CPUs?

Patience. It will happen.

thanks

ron

[Segher Boessenkool]

> As Hao is suspecting, AMD64 CAR won't work on Geode.
>
> There isn't anything in LB to do CAR (but it would be possible).

Could you give a quick description how cache-as-RAM
should be done on a Geode?  Nothing detailed, just
the outline.

Segher

[Tom Sylla]

Segher Boessenkool wrote:
> > As Hao is suspecting, AMD64 CAR won't work on Geode.
> >
> > There isn't anything in LB to do CAR (but it would be possible).
>
> Could you give a quick description how cache-as-RAM
> should be done on a Geode?  Nothing detailed, just
> the outline.

Well, the outline is the same as the one used for AMD64 CAR: "Cache 
Initialization For General Storage During Boot" in the BKDG.

The registers are all different though, so it is more of a translation. 
DRAM base/limit translate to routing in the GLIUs, MTRRS translate to 
RCONFs in the CPU.

The current CAR code modifies that cacheability rules and mappings with 
fixed, variable, and default type MTRRs. The code is generic, except for 
one AMD64-specific MSR. I don't see why it wouldn't work on any proc 
with x86-compatible MTRRs.

Geodes don't have compatible MTRRs, they have "Region Configs" (RCONFS). 
There are fixed, variable, and default RCONFs, so the functionality 
needed is all there. The RCONFs are MSR accessible, just like MTRRs, but 
they are not at the same addresses, and do not have the same 
definitions. The region configs are all documented in the GX and LX 
databooks.

[Segher Boessenkool]

> > Could you give a quick description how cache-as-RAM
> > should be done on a Geode?  Nothing detailed, just
> > the outline.
>
> Well, the outline is the same as the one used for AMD64 CAR: "Cache 
> Initialization For General Storage During Boot" in the BKDG.

What's the BKDG?
> The current CAR code modifies that cacheability rules and mappings 
> with fixed, variable, and default type MTRRs. The code is generic, 
> except for one AMD64-specific MSR.

So it's the same "put stuff into the cache, then mark that memory
range as uncacheable" trick?
> I don't see why it wouldn't work on any proc with x86-compatible 
> MTRRs.

I could come up with some scenarios but none look very realistic.
For example, the cache could do some "background" writebacks to
try to optimise performance.  Unfortunately the public documentation
for x86 CPUs (any vendor) never seems to describe the caches'
behaviour in detail.

Thanks for the explanation,

Segher

[Stefan Reinauer]

* Segher Boessenkool  [070408 14:54]:
> > > Could you give a quick description how cache-as-RAM
> > > should be done on a Geode?  Nothing detailed, just
> > > the outline.
> >
> > Well, the outline is the same as the one used for AMD64 CAR: "Cache 
> > Initialization For General Storage During Boot" in the BKDG.
>
> What's the BKDG?

bios and kernel developers guide.

[Segher Boessenkool]

> > What's the BKDG?
>
> bios and kernel developers guide.

Oh of course, thanks :-)

Segher