r3053 - in trunk/coreboot-v2: . documentation documentation/RFC src/arch/i386 src/arch/i386/boot src/arch/i386/include/arch src/arch/i386/init src/arch/i386/lib src/arch/ppc src/arch/ppc/boot src/arch/ppc/init src/boot src/config src/console src/cpu/amd/car src/cpu/amd/model_gx2 src/cpu/amd/model_lx src/cpu/amd/sc520 src/cpu/emulation/qemu-i386 src/cpu/ppc/mpc74xx src/cpu/ppc/ppc4xx src/cpu/ppc/ppc7xx src/cpu/x86/32bit src/cpu/x86/car src/cpu/x86/lapic src/cpu/x86/pae src/devices/emulator/x86emu
Author: stepan Date: 2008-01-18 16:08:58 +0100 (Fri, 18 Jan 2008) New Revision: 3053
Modified: trunk/coreboot-v2/NEWS trunk/coreboot-v2/README trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex trunk/coreboot-v2/documentation/RFC/config.tex trunk/coreboot-v2/src/arch/i386/Config.lb trunk/coreboot-v2/src/arch/i386/boot/acpi.c trunk/coreboot-v2/src/arch/i386/boot/boot.c trunk/coreboot-v2/src/arch/i386/boot/linuxbios_table.c trunk/coreboot-v2/src/arch/i386/boot/linuxbios_table.h trunk/coreboot-v2/src/arch/i386/boot/tables.c trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb trunk/coreboot-v2/src/arch/i386/init/ldscript.lb trunk/coreboot-v2/src/arch/i386/init/ldscript_apc.lb trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb trunk/coreboot-v2/src/arch/i386/lib/c_start.S trunk/coreboot-v2/src/arch/i386/lib/console.c trunk/coreboot-v2/src/arch/ppc/Config.lb trunk/coreboot-v2/src/arch/ppc/boot/boot.c trunk/coreboot-v2/src/arch/ppc/boot/linuxbios_table.c trunk/coreboot-v2/src/arch/ppc/boot/linuxbios_table.h trunk/coreboot-v2/src/arch/ppc/boot/tables.c trunk/coreboot-v2/src/arch/ppc/init/ldscript.lb trunk/coreboot-v2/src/boot/elfboot.c trunk/coreboot-v2/src/boot/filo.c trunk/coreboot-v2/src/boot/hardwaremain.c trunk/coreboot-v2/src/config/Config.lb trunk/coreboot-v2/src/config/LinuxBIOSDoc.config trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/config/doxyscript.base trunk/coreboot-v2/src/config/linuxbios_apc.ld trunk/coreboot-v2/src/config/linuxbios_ram.ld trunk/coreboot-v2/src/console/btext_console.c trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c trunk/coreboot-v2/src/cpu/amd/car/disable_cache_as_ram.c trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c trunk/coreboot-v2/src/cpu/amd/model_gx2/vsmsetup.c trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc trunk/coreboot-v2/src/cpu/amd/model_lx/vsmsetup.c trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c trunk/coreboot-v2/src/cpu/emulation/qemu-i386/northbridge.c trunk/coreboot-v2/src/cpu/ppc/mpc74xx/Config.lb trunk/coreboot-v2/src/cpu/ppc/mpc74xx/mpc74xx.inc trunk/coreboot-v2/src/cpu/ppc/ppc4xx/Config.lb trunk/coreboot-v2/src/cpu/ppc/ppc7xx/Config.lb trunk/coreboot-v2/src/cpu/ppc/ppc7xx/ppc7xx.inc trunk/coreboot-v2/src/cpu/x86/32bit/entry32.inc trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c trunk/coreboot-v2/src/devices/emulator/x86emu/sys.c trunk/coreboot-v2/src/drivers/ati/ragexl/xlinit.c trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c trunk/coreboot-v2/src/include/boot/elf.h trunk/coreboot-v2/src/include/boot/linuxbios_tables.h trunk/coreboot-v2/src/include/console/btext.h trunk/coreboot-v2/src/include/device/pci_ids.h trunk/coreboot-v2/src/include/version.h trunk/coreboot-v2/src/include/x86emu/x86emu.h trunk/coreboot-v2/src/lib/lzma.c trunk/coreboot-v2/src/lib/usbdebug_direct.c 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trunk/coreboot-v2/targets/iwill/dk8x/Config.lb trunk/coreboot-v2/targets/lippert/frontrunner/Config.lb trunk/coreboot-v2/targets/momentum/apache/Config.lb trunk/coreboot-v2/targets/motorola/sandpoint/Config.lb trunk/coreboot-v2/targets/motorola/sandpoint/Config.lb.ide_stream trunk/coreboot-v2/targets/msi/ms6178/Config.lb trunk/coreboot-v2/targets/msi/ms7260/Config-abuild.lb trunk/coreboot-v2/targets/msi/ms7260/Config.lb trunk/coreboot-v2/targets/msi/ms9185/Config-abuild.lb trunk/coreboot-v2/targets/msi/ms9185/Config.lb trunk/coreboot-v2/targets/msi/ms9282/Config-abuild.lb trunk/coreboot-v2/targets/msi/ms9282/Config.lb trunk/coreboot-v2/targets/newisys/khepri/Config.lb trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config.lb trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config.lb.kernel trunk/coreboot-v2/targets/olpc/btest/Config.lb trunk/coreboot-v2/targets/olpc/rev_a/Config.1M.lb trunk/coreboot-v2/targets/olpc/rev_a/Config.SPI.lb trunk/coreboot-v2/targets/olpc/rev_a/Config.kernel.lb trunk/coreboot-v2/targets/olpc/rev_a/Config.lb trunk/coreboot-v2/targets/pcengines/alix1c/Config.lb trunk/coreboot-v2/targets/sunw/ultra40/Config.lb trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb.kernel trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb trunk/coreboot-v2/targets/technologic/ts5300/Config.lb trunk/coreboot-v2/targets/totalimpact/briq/Config.lb trunk/coreboot-v2/targets/tyan/s1846/Config.lb trunk/coreboot-v2/targets/tyan/s2735/Config.lb trunk/coreboot-v2/targets/tyan/s2735/ns2735 trunk/coreboot-v2/targets/tyan/s2850/Config.lb trunk/coreboot-v2/targets/tyan/s2850/ns2850 trunk/coreboot-v2/targets/tyan/s2875/Config.lb trunk/coreboot-v2/targets/tyan/s2875/ns2875 trunk/coreboot-v2/targets/tyan/s2880/Config.lb trunk/coreboot-v2/targets/tyan/s2880/ns2880 trunk/coreboot-v2/targets/tyan/s2881/Config.lb trunk/coreboot-v2/targets/tyan/s2881/ns2881 trunk/coreboot-v2/targets/tyan/s2882/Config.lb trunk/coreboot-v2/targets/tyan/s2882/ns2882 trunk/coreboot-v2/targets/tyan/s2885/Config.lb trunk/coreboot-v2/targets/tyan/s2885/ns2885 trunk/coreboot-v2/targets/tyan/s2891/Config.lb trunk/coreboot-v2/targets/tyan/s2891/Config.lb.com2 trunk/coreboot-v2/targets/tyan/s2892/Config.lb trunk/coreboot-v2/targets/tyan/s2895/Config.lb trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb trunk/coreboot-v2/targets/tyan/s2912/Config.lb trunk/coreboot-v2/targets/tyan/s2912/Config.lb.kernel trunk/coreboot-v2/targets/tyan/s4880/Config.lb trunk/coreboot-v2/targets/tyan/s4880/ns4880 trunk/coreboot-v2/targets/tyan/s4882/Config.lb trunk/coreboot-v2/targets/tyan/s4882/ns4882 trunk/coreboot-v2/targets/via/epia-m/Config-abuild.lb trunk/coreboot-v2/targets/via/epia-m/Config.512kflash.lb trunk/coreboot-v2/targets/via/epia-m/Config.etherboot.lb trunk/coreboot-v2/targets/via/epia-m/Config.filo.lb trunk/coreboot-v2/targets/via/epia-m/Config.lb trunk/coreboot-v2/targets/via/epia-m/Config.vga.filo trunk/coreboot-v2/targets/via/epia/Config.512kflash.lb trunk/coreboot-v2/targets/via/epia/Config.512kflash.linuxtiny.lb trunk/coreboot-v2/targets/via/epia/Config.filo.lb trunk/coreboot-v2/targets/via/epia/Config.ituner.filo.lb trunk/coreboot-v2/targets/via/epia/Config.lb trunk/coreboot-v2/util/ADLO/CAST trunk/coreboot-v2/util/ADLO/HACKING trunk/coreboot-v2/util/ADLO/INSTALL trunk/coreboot-v2/util/ADLO/README trunk/coreboot-v2/util/ADLO/STATUS trunk/coreboot-v2/util/ADLO/bochs/bios/rombios.c trunk/coreboot-v2/util/ADLO/loader.s trunk/coreboot-v2/util/abuild/abuild trunk/coreboot-v2/util/abuild/abuild.1 trunk/coreboot-v2/util/analysis/Makefile trunk/coreboot-v2/util/buildrom/buildrom.c trunk/coreboot-v2/util/lbtdump/README trunk/coreboot-v2/util/lbtdump/lbtdump.c trunk/coreboot-v2/util/newconfig/config.g trunk/coreboot-v2/util/optionlist/Options-wiki.xsl trunk/coreboot-v2/util/optionlist/Options.xsl trunk/coreboot-v2/util/optionlist/README trunk/coreboot-v2/util/optionlist/mkOptionList.py trunk/coreboot-v2/util/romcc/romcc.1 Log: Rename almost all occurences of LinuxBIOS to coreboot. Due to the automatic nature of this update, I am self-acking. It worked in abuild.
Signed-off-by: Stefan Reinauer stepan@coresystems.de Acked-by: Stefan Reinauer stepan@coresystems.de
Modified: trunk/coreboot-v2/NEWS =================================================================== --- trunk/coreboot-v2/NEWS 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/NEWS 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ - 2.0.0 - this NEWS file is neglected in favor of the svn commit logs. - See http://snapshots.linuxbios.org/ + See http://tracker.coreboot.org/ - 1.1.8 - Store everything in arch - 1.1.7
Modified: trunk/coreboot-v2/README =================================================================== --- trunk/coreboot-v2/README 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/README 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,8 +1,8 @@ ------------------------------------------------------------------------------- -LinuxBIOS README +Coreboot README -------------------------------------------------------------------------------
-LinuxBIOS is a Free Software project aimed at replacing the proprietary +Coreboot is a Free Software project aimed at replacing the proprietary BIOS you can find in most of today's computers.
It performs just a little bit of hardware initialization and then executes @@ -13,7 +13,7 @@ --------
After the basic initialization of the hardware has been performed, any -desired "payload" can be started by LinuxBIOS. Examples include: +desired "payload" can be started by coreboot. Examples include:
* A Linux kernel * FILO (a simple bootloader with filesystem support) @@ -31,39 +31,39 @@ Supported Hardware ------------------
-LinuxBIOS supports a wide range of chipsets, devices, and mainboards. +Coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
- * http://www.linuxbios.org/Supported_Motherboards - * http://www.linuxbios.org/Supported_Chipsets_and_Devices + * http://www.coreboot.org/Supported_Motherboards + * http://www.coreboot.org/Supported_Chipsets_and_Devices
Website and Mailing List ------------------------
Further details on the project, a FAQ, many HOWTOs, news, development -guidelines and more can be found on the LinuxBIOS website: +guidelines and more can be found on the coreboot website:
- http://www.linuxbios.org + http://www.coreboot.org
-You can contact us directly on the LinuxBIOS mailing list: +You can contact us directly on the coreboot mailing list:
- http://www.linuxbios.org/Mailinglist + http://www.coreboot.org/Mailinglist
Copyright and License ---------------------
-The copyright on LinuxBIOS is owned by quite a large number of individual +The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
-LinuxBIOS is licensed under the terms of the GNU General Public License (GPL). +Coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files (mostly those derived from the Linux kernel) are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
-This makes the resulting LinuxBIOS images licensed under the GPL, version 2. +This makes the resulting coreboot images licensed under the GPL, version 2.
Modified: trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex =================================================================== --- trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex 2008-01-18 15:08:58 UTC (rev 3053) @@ -374,7 +374,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" mainboard amd/solo payload /suse/stepan/tg3ide_ disk.zelf @@ -471,7 +471,7 @@
Default image size. Defaults to \texttt{65535} bytes.
-\item \begin{verbatim}LINUXBIOS_EXTRA_VERSION\end{verbatim} +\item \begin{verbatim}COREBOOT_EXTRA_VERSION\end{verbatim}
LinuxBIOS extra version. This option has an empty string as default. Set to any string to add an extra version string to your LinuxBIOS build.
Modified: trunk/coreboot-v2/documentation/RFC/config.tex =================================================================== --- trunk/coreboot-v2/documentation/RFC/config.tex 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/documentation/RFC/config.tex 2008-01-18 15:08:58 UTC (rev 3053) @@ -281,7 +281,7 @@ export HEAP_SIZE:=8192 export STACK_SIZE:=8192 export MEMORY_HOLE:=0 -export LINUXBIOS_VERSION:=1.1.0 +export COREBOOT_VERSION:=1.1.0 export CC:=$(CROSS_COMPILE)gcc
\end{verbatim}
Modified: trunk/coreboot-v2/src/arch/i386/Config.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -22,12 +22,12 @@ end
makerule all - depends "linuxbios.rom" + depends "coreboot.rom" end
makerule floppy depends "all" - action "mcopy -o linuxbios.rom a:" + action "mcopy -o coreboot.rom a:" end
makerule nrv2b @@ -55,7 +55,7 @@ # this one example shows the mess that has occurred. People are now mixing # conditional if in the make style with if in the config language style. # The -1 is linux standard. -# I don't much like it but it is the mode nowadays. So linuxbios will change +# I don't much like it but it is the mode nowadays. So coreboot will change # what a mess. -- RGM # catch the case where there is no compression makedefine PAYLOAD-1:=payload @@ -70,16 +70,16 @@ end
if USE_FAILOVER_IMAGE - makedefine LINUXBIOS_APC:= - makedefine LINUXBIOS_RAM_ROM:= + makedefine COREBOOT_APC:= + makedefine COREBOOT_RAM_ROM:=
- makerule linuxbios.rom - depends "linuxbios.strip" + makerule coreboot.rom + depends "coreboot.strip" action "cp $< $@" end else - makerule linuxbios.rom - depends "linuxbios.strip buildrom $(PAYLOAD-1)" + makerule coreboot.rom + depends "coreboot.strip buildrom $(PAYLOAD-1)" action "./buildrom $< $@ $(PAYLOAD-1) $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)" end end @@ -98,10 +98,10 @@ action "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o" end
- makerule linuxbios - depends "crt0.o init.o $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld" + makerule coreboot + depends "crt0.o init.o $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld" action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o" - action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map" + action "$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map" end
end
Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,5 +1,5 @@ /* - * LinuxBIOS ACPI Table support + * coreboot ACPI Table support * written by Stefan Reinauer stepan@openbios.org * (C) 2004 SUSE LINUX AG * (C) 2005 Stefan Reinauer
Modified: trunk/coreboot-v2/src/arch/i386/boot/boot.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/boot.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/boot/boot.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -113,8 +113,8 @@ " addl 12(%%esp), %%eax\n\t" " addl 8(%%esp), %%eax\n\t" " movl %%eax, 20(%%esp)\n\t" - /* Place a copy of linuxBIOS in it's new location */ - /* Move ``longs'' the linuxBIOS size is 4 byte aligned */ + /* Place a copy of coreboot in it's new location */ + /* Move ``longs'' the coreboot size is 4 byte aligned */ " movl 12(%%esp), %%edi\n\t" " addl 8(%%esp), %%edi\n\t" " movl 16(%%esp), %%esi\n\t" @@ -122,16 +122,16 @@ " shrl $2, %%ecx\n\t" " rep movsl\n\t"
- /* Adjust the stack pointer to point into the new linuxBIOS image */ + /* Adjust the stack pointer to point into the new coreboot image */ " addl 20(%%esp), %%esp\n\t" - /* Adjust the instruction pointer to point into the new linuxBIOS image */ + /* Adjust the instruction pointer to point into the new coreboot image */ " movl $1f, %%eax\n\t" " addl 20(%%esp), %%eax\n\t" " jmp *%%eax\n\t" "1: \n\t"
- /* Copy the linuxBIOS bounce buffer over linuxBIOS */ - /* Move ``longs'' the linuxBIOS size is 4 byte aligned */ + /* Copy the coreboot bounce buffer over coreboot */ + /* Move ``longs'' the coreboot size is 4 byte aligned */ " movl 16(%%esp), %%edi\n\t" " movl 12(%%esp), %%esi\n\t" " movl 8(%%esp), %%ecx\n\t" @@ -147,8 +147,8 @@ " cli \n\t" " cld \n\t"
- /* Copy the saved copy of linuxBIOS where linuxBIOS runs */ - /* Move ``longs'' the linuxBIOS size is 4 byte aligned */ + /* Copy the saved copy of coreboot where coreboot runs */ + /* Move ``longs'' the coreboot size is 4 byte aligned */ " movl 16(%%esp), %%edi\n\t" " movl 12(%%esp), %%esi\n\t" " addl 8(%%esp), %%esi\n\t" @@ -156,10 +156,10 @@ " shrl $2, %%ecx\n\t" " rep movsl\n\t"
- /* Adjust the stack pointer to point into the old linuxBIOS image */ + /* Adjust the stack pointer to point into the old coreboot image */ " subl 20(%%esp), %%esp\n\t"
- /* Adjust the instruction pointer to point into the old linuxBIOS image */ + /* Adjust the instruction pointer to point into the old coreboot image */ " movl $1f, %%eax\n\t" " subl 20(%%esp), %%eax\n\t" " jmp *%%eax\n\t"
Modified: trunk/coreboot-v2/src/arch/i386/boot/linuxbios_table.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/linuxbios_table.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/boot/linuxbios_table.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -122,16 +122,16 @@ uint32_t tag; const char *string; } strings[] = { - { LB_TAG_VERSION, linuxbios_version, }, - { LB_TAG_EXTRA_VERSION, linuxbios_extra_version, }, - { LB_TAG_BUILD, linuxbios_build, }, - { LB_TAG_COMPILE_TIME, linuxbios_compile_time, }, - { LB_TAG_COMPILE_BY, linuxbios_compile_by, }, - { LB_TAG_COMPILE_HOST, linuxbios_compile_host, }, - { LB_TAG_COMPILE_DOMAIN, linuxbios_compile_domain, }, - { LB_TAG_COMPILER, linuxbios_compiler, }, - { LB_TAG_LINKER, linuxbios_linker, }, - { LB_TAG_ASSEMBLER, linuxbios_assembler, }, + { LB_TAG_VERSION, coreboot_version, }, + { LB_TAG_EXTRA_VERSION, coreboot_extra_version, }, + { LB_TAG_BUILD, coreboot_build, }, + { LB_TAG_COMPILE_TIME, coreboot_compile_time, }, + { LB_TAG_COMPILE_BY, coreboot_compile_by, }, + { LB_TAG_COMPILE_HOST, coreboot_compile_host, }, + { LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, }, + { LB_TAG_COMPILER, coreboot_compiler, }, + { LB_TAG_LINKER, coreboot_linker, }, + { LB_TAG_ASSEMBLER, coreboot_assembler, }, }; unsigned int i; for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) { @@ -201,7 +201,7 @@ head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes); head->header_checksum = 0; head->header_checksum = compute_ip_checksum(head, sizeof(*head)); - printk_debug("Wrote linuxbios table at: %p - %p checksum %lx\n", + printk_debug("Wrote coreboot table at: %p - %p checksum %lx\n", head, rec, head->table_checksum); return (unsigned long)rec; } @@ -315,8 +315,8 @@ lb_cleanup_memory_ranges(mem); }
-/* Routines to extract part so the linuxBIOS table or - * information from the linuxBIOS table after we have written it. +/* Routines to extract part so the coreboot table or + * information from the coreboot table after we have written it. * Currently get_lb_mem relies on a global we can change the * implementaiton. */ @@ -348,7 +348,7 @@ return mem; }
-unsigned long write_linuxbios_table( +unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end) { @@ -383,7 +383,7 @@ rec_dest = lb_new_record(head); rec_src = (struct lb_record *)(void *)&option_table; memcpy(rec_dest, rec_src, rec_src->size); - /* Create cmos checksum entry in linuxbios table */ + /* Create cmos checksum entry in coreboot table */ lb_cmos_checksum(head); } #endif @@ -401,9 +401,9 @@
/* Note: * I assume that there is always memory at immediately after - * the low_table_end. This means that after I setup the linuxbios table. + * the low_table_end. This means that after I setup the coreboot table. * I can trivially fixup the reserved memory ranges to hold the correct - * size of the linuxbios table. + * size of the coreboot table. */
/* Record our motheboard */
Modified: trunk/coreboot-v2/src/arch/i386/boot/linuxbios_table.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/linuxbios_table.h 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/boot/linuxbios_table.h 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,10 +1,10 @@ -#ifndef LINUXBIOS_TABLE_H -#define LINUXBIOS_TABLE_H +#ifndef COREBOOT_TABLE_H +#define COREBOOT_TABLE_H
#include <boot/linuxbios_tables.h>
-/* This file holds function prototypes for building the linuxbios table. */ -unsigned long write_linuxbios_table( +/* This file holds function prototypes for building the coreboot table. */ +unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end);
@@ -19,11 +19,11 @@ struct lb_mainboard *lb_mainboard(struct lb_header *header); unsigned long lb_table_fini(struct lb_header *header);
-/* Routines to extract part so the linuxBIOS table or information - * from the linuxBIOS table. +/* Routines to extract part so the coreboot table or information + * from the coreboot table. */ struct lb_memory *get_lb_mem(void);
extern struct cmos_option_table option_table;
-#endif /* LINUXBIOS_TABLE_H */ +#endif /* COREBOOT_TABLE_H */
Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -23,7 +23,7 @@
// Copy GDT to new location and reload it // 2003-07 by SONE Takeshi -// Ported from Etherboot to LinuxBIOS 2005-08 by Steve Magnani +// Ported from Etherboot to coreboot 2005-08 by Steve Magnani void move_gdt(unsigned long newgdt) { uint16_t num_gdt_bytes = &gdt_end - &gdt; @@ -58,7 +58,7 @@
/* Write ACPI tables */ /* write them in the rom area because DSDT can be large (8K on epia-m) which - * pushes linuxbios table out of first 4K if set up in low table area + * pushes coreboot table out of first 4K if set up in low table area */ rom_table_end = write_acpi_tables(rom_table_end); rom_table_end = (rom_table_end+1023) & ~1023; @@ -105,8 +105,8 @@ move_gdt(low_table_end); low_table_end += &gdt_end - &gdt;
- /* The linuxbios table must be in 0-4K or 960K-1M */ - write_linuxbios_table(low_table_start, low_table_end, + /* The coreboot table must be in 0-4K or 960K-1M */ + write_coreboot_table(low_table_start, low_table_end, rom_table_start, rom_table_end);
return get_lb_mem();
Modified: trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,5 +1,5 @@ /* - * Initial LinuxBIOS ACPI Support - headers and defines. + * coreboot ACPI Support - headers and defines. * * written by Stefan Reinauer stepan@openbios.org * (C) 2004 SUSE LINUX AG
Modified: trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h 2008-01-18 15:08:58 UTC (rev 3053) @@ -84,7 +84,7 @@
typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */
-/* FIXME: We need to make the LinuxBIOS to run at 64bit mode, So when read/write memory above 4G, +/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access */
Modified: trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -16,7 +16,7 @@ * * - Converted to gas assembly, and refitted to work with etherboot. * Eric Biederman 20 Aug 2002 - * - Merged the nrv2b decompressor into crt0.base of LinuxBIOS + * - Merged the nrv2b decompressor into crt0.base of coreboot * Eric Biederman 26 Sept 2002 */
@@ -65,7 +65,7 @@
cld /* clear direction flag */ - /* copy linuxBIOS from it's initial load location to + /* copy coreboot from it's initial load location to * the location it is compiled to run at. * Normally this is copying from FLASH ROM to RAM. */ @@ -215,8 +215,8 @@
#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) .section ".rom.data" -str_copying_to_ram: .string "Copying LinuxBIOS to RAM.\r\n" -str_pre_main: .string "Jumping to LinuxBIOS.\r\n" +str_copying_to_ram: .string "Copying coreboot to RAM.\r\n" +str_pre_main: .string "Jumping to coreboot.\r\n" .previous
#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/init/ldscript.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/init/ldscript.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -7,7 +7,7 @@ * : heap * : stack * _ROMBASE - * : linuxbios text + * : coreboot text * : readonly text */ /* @@ -32,14 +32,14 @@ */
TARGET(binary) -INPUT(linuxbios_ram.rom) +INPUT(coreboot_ram.rom) SECTIONS { . = _ROMBASE;
.ram . : { _ram = . ; - linuxbios_ram.rom(*) + coreboot_ram.rom(*) _eram = . ; }
Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript_apc.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/init/ldscript_apc.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/init/ldscript_apc.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,9 +1,9 @@ -INPUT(linuxbios_apc.rom) +INPUT(coreboot_apc.rom) SECTIONS { .apcrom . : { _apcrom = .; - linuxbios_apc.rom(*) + coreboot_apc.rom(*) _eapcrom = .; } _iseg_apc = DCACHE_RAM_BASE;
Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -7,7 +7,7 @@ * : heap * : stack * _ROMBASE - * : linuxbios text + * : coreboot text * : readonly text */ /*
Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -7,7 +7,7 @@ * : heap * : stack * _ROMBASE - * : linuxbios text + * : coreboot text * : readonly text */ /* @@ -32,14 +32,14 @@ */
TARGET(binary) -INPUT(linuxbios_ram.rom) +INPUT(coreboot_ram.rom) SECTIONS { . = _ROMBASE;
.ram . : { _ram = . ; - linuxbios_ram.rom(*) + coreboot_ram.rom(*) _eram = . ; }
Modified: trunk/coreboot-v2/src/arch/i386/lib/c_start.S =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/c_start.S 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/lib/c_start.S 2008-01-18 15:08:58 UTC (rev 3053) @@ -251,8 +251,8 @@
.data
- /* This is the gdt for GCC part of LinuxBIOS. - * It is different from the gdt in ROMCC/ASM part of LinuxBIOS + /* This is the gdt for GCC part of coreboot. + * It is different from the gdt in ROMCC/ASM part of coreboot * which is defined in entry32.inc */ gdt: /* selgdt 0, unused */
Modified: trunk/coreboot-v2/src/arch/i386/lib/console.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/console.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/i386/lib/console.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -19,19 +19,19 @@
#endif /* CONFIG_USE_PRINTK_IN_CAR */
-#ifndef LINUXBIOS_EXTRA_VERSION -#define LINUXBIOS_EXTRA_VERSION "" +#ifndef COREBOOT_EXTRA_VERSION +#define COREBOOT_EXTRA_VERSION "" #endif
static void console_init(void) { static const char console_test[] = - "\r\n\r\nLinuxBIOS-" - LINUXBIOS_VERSION - LINUXBIOS_EXTRA_VERSION + "\r\n\r\ncoreboot-" + COREBOOT_VERSION + COREBOOT_EXTRA_VERSION " " - LINUXBIOS_BUILD + COREBOOT_BUILD " starting...\r\n"; print_info(console_test); }
Modified: trunk/coreboot-v2/src/arch/ppc/Config.lb =================================================================== --- trunk/coreboot-v2/src/arch/ppc/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/ppc/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,7 +1,7 @@ ldscript init/ldscript.lb
-makerule linuxbios.rom - depends "linuxbios" +makerule coreboot.rom + depends "coreboot" action "cp $< $@" end
Modified: trunk/coreboot-v2/src/arch/ppc/boot/boot.c =================================================================== --- trunk/coreboot-v2/src/arch/ppc/boot/boot.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/ppc/boot/boot.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -29,7 +29,7 @@ */ flush_dcache();
- /* On ppc we don't currently support loading over LinuxBIOS. + /* On ppc we don't currently support loading over coreboot. * So ignore the buffer. */
Modified: trunk/coreboot-v2/src/arch/ppc/boot/linuxbios_table.c =================================================================== --- trunk/coreboot-v2/src/arch/ppc/boot/linuxbios_table.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/ppc/boot/linuxbios_table.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -104,16 +104,16 @@ uint32_t tag; const uint8_t *string; } strings[] = { - { LB_TAG_VERSION, linuxbios_version, }, - { LB_TAG_EXTRA_VERSION, linuxbios_extra_version, }, - { LB_TAG_BUILD, linuxbios_build, }, - { LB_TAG_COMPILE_TIME, linuxbios_compile_time, }, - { LB_TAG_COMPILE_BY, linuxbios_compile_by, }, - { LB_TAG_COMPILE_HOST, linuxbios_compile_host, }, - { LB_TAG_COMPILE_DOMAIN, linuxbios_compile_domain, }, - { LB_TAG_COMPILER, linuxbios_compiler, }, - { LB_TAG_LINKER, linuxbios_linker, }, - { LB_TAG_ASSEMBLER, linuxbios_assembler, }, + { LB_TAG_VERSION, coreboot_version, }, + { LB_TAG_EXTRA_VERSION, coreboot_extra_version, }, + { LB_TAG_BUILD, coreboot_build, }, + { LB_TAG_COMPILE_TIME, coreboot_compile_time, }, + { LB_TAG_COMPILE_BY, coreboot_compile_by, }, + { LB_TAG_COMPILE_HOST, coreboot_compile_host, }, + { LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, }, + { LB_TAG_COMPILER, coreboot_compiler, }, + { LB_TAG_LINKER, coreboot_linker, }, + { LB_TAG_ASSEMBLER, coreboot_assembler, }, }; unsigned int i; for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) { @@ -183,7 +183,7 @@ head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes); head->header_checksum = 0; head->header_checksum = compute_ip_checksum(head, sizeof(*head)); - printk_debug("Wrote linuxbios table at: %p - %p checksum %lx\n", + printk_debug("Wrote coreboot table at: %p - %p checksum %lx\n", head, rec, head->table_checksum); return (unsigned long)rec; } @@ -297,8 +297,8 @@ lb_cleanup_memory_ranges(mem); }
-/* Routines to extract part so the linuxBIOS table or - * information from the linuxBIOS table after we have written it. +/* Routines to extract part so the coreboot table or + * information from the coreboot table after we have written it. * Currently get_lb_mem relies on a global we can change the * implementaiton. */ @@ -330,7 +330,7 @@ return mem; }
-unsigned long write_linuxbios_table( +unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end) { @@ -363,9 +363,9 @@
/* Note: * I assume that there is always memory at immediately after - * the low_table_end. This means that after I setup the linuxbios table. + * the low_table_end. This means that after I setup the coreboot table. * I can trivially fixup the reserved memory ranges to hold the correct - * size of the linuxbios table. + * size of the coreboot table. */
/* Record our motheboard */
Modified: trunk/coreboot-v2/src/arch/ppc/boot/linuxbios_table.h =================================================================== --- trunk/coreboot-v2/src/arch/ppc/boot/linuxbios_table.h 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/ppc/boot/linuxbios_table.h 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,12 +1,12 @@ -#ifndef LINUXBIOS_TABLE_H -#define LINUXBIOS_TABLE_H +#ifndef COREBOOT_TABLE_H +#define COREBOOT_TABLE_H
#include <boot/linuxbios_tables.h>
struct mem_range;
-/* This file holds function prototypes for building the linuxbios table. */ -unsigned long write_linuxbios_table( +/* This file holds function prototypes for building the coreboot table. */ +unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end);
@@ -21,11 +21,11 @@ struct lb_mainboard *lb_mainboard(struct lb_header *header); unsigned long lb_table_fini(struct lb_header *header);
-/* Routines to extract part so the linuxBIOS table or information - * from the linuxBIOS table. +/* Routines to extract part so the coreboot table or information + * from the coreboot table. */ struct lb_memory *get_lb_mem(void);
extern struct cmos_option_table option_table;
-#endif /* LINUXBIOS_TABLE_H */ +#endif /* COREBOOT_TABLE_H */
Modified: trunk/coreboot-v2/src/arch/ppc/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/ppc/boot/tables.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/ppc/boot/tables.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -18,8 +18,8 @@ low_table_start = 0; low_table_end = 16;
- /* The linuxbios table must be in 0-4K or 960K-1M */ - write_linuxbios_table( + /* The coreboot table must be in 0-4K or 960K-1M */ + write_coreboot_table( low_table_start, low_table_end, rom_table_start, rom_table_end);
Modified: trunk/coreboot-v2/src/arch/ppc/init/ldscript.lb =================================================================== --- trunk/coreboot-v2/src/arch/ppc/init/ldscript.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/arch/ppc/init/ldscript.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -5,7 +5,7 @@ * _RESET : reset vector (may be at top of ROM) * _EXCEPTIONS_VECTORS : exception table * - * _ROMSTART : linuxbios text + * _ROMSTART : coreboot text * : payload text * * _RAMBASE : address to copy payload @@ -26,7 +26,7 @@ ENTRY(_start)
TARGET(binary) -INPUT(linuxbios_ram.rom) +INPUT(coreboot_ram.rom) SECTIONS { /* @@ -54,7 +54,7 @@ }
/* - * Absolute location of LinuxBIOS initialization code in ROM. + * Absolute location of coreboot initialization code in ROM. */ . = _ROMSTART; .rom . : { @@ -63,7 +63,7 @@ *(.text); *(.rom.data); *(.rodata); - *(EXCLUDE_FILE(linuxbios_ram.rom) .data); + *(EXCLUDE_FILE(coreboot_ram.rom) .data); . = ALIGN(16); _erom = .; } @@ -71,16 +71,16 @@ _elrom = LOADADDR(.rom) + SIZEOF(.rom); /* - * Ram is the LinuxBIOS code that runs from RAM. + * Ram is the coreboot code that runs from RAM. */ .ram . : { _ram = . ; - linuxbios_ram.rom(*) + coreboot_ram.rom(*) _eram = . ; }
/* - * Absolute location of where LinuxBIOS will be relocated in RAM. + * Absolute location of where coreboot will be relocated in RAM. */ _iseg = _RAMBASE; _eiseg = _iseg + SIZEOF(.ram);
Modified: trunk/coreboot-v2/src/boot/elfboot.c =================================================================== --- trunk/coreboot-v2/src/boot/elfboot.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/boot/elfboot.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -9,7 +9,7 @@ #include <stdlib.h> #include <string.h>
-/* Maximum physical address we can use for the linuxBIOS bounce buffer. +/* Maximum physical address we can use for the coreboot bounce buffer. */ #ifndef MAX_ADDR #define MAX_ADDR -1UL @@ -88,16 +88,16 @@ * a machine, and implementing general relocation is hard. * * The solution: - * - Allocate a buffer twice the size of the linuxBIOS image. - * - Anything that would overwrite linuxBIOS copy into the lower half of + * - Allocate a buffer twice the size of the coreboot image. + * - Anything that would overwrite coreboot copy into the lower half of * the buffer. - * - After loading an ELF image copy linuxBIOS to the upper half of the + * - After loading an ELF image copy coreboot to the upper half of the * buffer. * - Then jump to the loaded image. * * Benefits: * - Nearly arbitrary standalone executables can be loaded. - * - LinuxBIOS is preserved, so it can be returned to. + * - Coreboot is preserved, so it can be returned to. * - The implementation is still relatively simple, * and much simpler then the general case implemented in kexec. * @@ -110,7 +110,7 @@ unsigned long buffer; int i; lb_size = (unsigned long)(&_eram_seg - &_ram_seg); - /* Double linuxBIOS size so I have somewhere to place a copy to return to */ + /* Double coreboot size so I have somewhere to place a copy to return to */ lb_size = lb_size + lb_size; mem_entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); buffer = 0; @@ -251,7 +251,7 @@
static void relocate_segment(unsigned long buffer, struct segment *seg) { - /* Modify all segments that want to load onto linuxBIOS + /* Modify all segments that want to load onto coreboot * to load onto the bounce buffer instead. */ unsigned long lb_start = (unsigned long)&_ram_seg; @@ -264,7 +264,7 @@ start = seg->s_addr; middle = start + seg->s_filesz; end = start + seg->s_memsz; - /* I don't conflict with linuxBIOS so get out of here */ + /* I don't conflict with coreboot so get out of here */ if ((end <= lb_start) || (start >= lb_end)) return;
@@ -272,7 +272,7 @@ start, middle, end);
/* Slice off a piece at the beginning - * that doesn't conflict with linuxBIOS. + * that doesn't conflict with coreboot. */ if (start < lb_start) { struct segment *new; @@ -311,7 +311,7 @@ } /* Slice off a piece at the end - * that doesn't conflict with linuxBIOS + * that doesn't conflict with coreboot */ if (end > lb_end) { unsigned long len = lb_end - start; @@ -545,7 +545,7 @@ struct verify_callback *cb_chain; unsigned long bounce_buffer;
- /* Find a bounce buffer so I can load to linuxBIOS's current location */ + /* Find a bounce buffer so I can load to coreboot's current location */ bounce_buffer = get_bounce_buffer(mem); if (!bounce_buffer) { printk_err("Could not find a bounce buffer...\n");
Modified: trunk/coreboot-v2/src/boot/filo.c =================================================================== --- trunk/coreboot-v2/src/boot/filo.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/boot/filo.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -2,7 +2,7 @@ * Copyright (C) 2003 by SONE Takeshi ts1@tsn.or.jp and others. * This program is licensed under the terms of GNU General Public License. * - * Modified for LinuxBIOS by Greg Watson gwatson@lanl.gov + * Modified for coreboot by Greg Watson gwatson@lanl.gov */
#include <console/console.h>
Modified: trunk/coreboot-v2/src/boot/hardwaremain.c =================================================================== --- trunk/coreboot-v2/src/boot/hardwaremain.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/boot/hardwaremain.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -22,7 +22,7 @@
/* - * C Bootstrap code for the LinuxBIOS + * C Bootstrap code for the coreboot */
@@ -38,9 +38,9 @@ #include <boot/elf.h>
/** - * @brief Main function of the DRAM part of LinuxBIOS. + * @brief Main function of the DRAM part of coreboot. * - * LinuxBIOS is divided into Pre-DRAM part and DRAM part. + * Coreboot is divided into Pre-DRAM part and DRAM part. * * * Device Enumeration: @@ -57,8 +57,8 @@ post_code(0x39);
- printk_notice("LinuxBIOS-%s%s %s %s...\n", - linuxbios_version, linuxbios_extra_version, linuxbios_build, + printk_notice("coreboot-%s%s %s %s...\n", + coreboot_version, coreboot_extra_version, coreboot_build, (boot_complete)?"rebooting":"booting");
post_code(0x40);
Modified: trunk/coreboot-v2/src/config/Config.lb =================================================================== --- trunk/coreboot-v2/src/config/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/config/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -27,102 +27,102 @@ # action "perl -e 'foreach $$var (split(" ", $$ENV{VARIABLES})) { if ($$ENV{$$var} =~ m/^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$$/) { print "$$var = $$ENV{$$var};\n"; }}' > $@" #end
-makerule linuxbios.strip - depends "linuxbios" - action "$(OBJCOPY) -O binary linuxbios linuxbios.strip" +makerule coreboot.strip + depends "coreboot" + action "$(OBJCOPY) -O binary coreboot coreboot.strip" end
-makerule linuxbios.a +makerule coreboot.a depends "$(OBJECTS)" - action "rm -f linuxbios.a" - action "ar cr linuxbios.a $(OBJECTS)" + action "rm -f coreboot.a" + action "ar cr coreboot.a $(OBJECTS)" end
-makerule linuxbios_ram.o - depends "$(DRIVER) linuxbios.a $(LIBGCC_FILE_NAME)" - action "$(CC) -nostdlib -r -o $@ c_start.o $(DRIVER) linuxbios.a $(LIBGCC_FILE_NAME)" +makerule coreboot_ram.o + depends "$(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" + action "$(CC) -nostdlib -r -o $@ c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" end
-makerule linuxbios_ram - depends "linuxbios_ram.o $(TOP)/src/config/linuxbios_ram.ld ldoptions" - action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_ram.ld linuxbios_ram.o" - action "$(CROSS_COMPILE)nm -n linuxbios_ram | sort > linuxbios_ram.map" +makerule coreboot_ram + depends "coreboot_ram.o $(TOP)/src/config/linuxbios_ram.ld ldoptions" + action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_ram.ld coreboot_ram.o" + action "$(CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map" end
## -## By default compress the part of linuxbios that runs from RAM +## By default compress the part of coreboot that runs from RAM ## -makedefine LINUXBIOS_RAM-$(CONFIG_COMPRESS):=linuxbios_ram.nrv2b -makedefine LINUXBIOS_RAM-$(CONFIG_UNCOMPRESSED):=linuxbios_ram.bin +makedefine COREBOOT_RAM-$(CONFIG_COMPRESS):=coreboot_ram.nrv2b +makedefine COREBOOT_RAM-$(CONFIG_UNCOMPRESSED):=coreboot_ram.bin
-makerule linuxbios_ram.bin - depends "linuxbios_ram" +makerule coreboot_ram.bin + depends "coreboot_ram" action "$(OBJCOPY) -O binary $< $@" end
-makerule linuxbios_ram.nrv2b - depends "linuxbios_ram.bin nrv2b" +makerule coreboot_ram.nrv2b + depends "coreboot_ram.bin nrv2b" action "./nrv2b e $< $@" end
-makerule linuxbios_ram.rom - depends "$(LINUXBIOS_RAM-1)" - action "cp $(LINUXBIOS_RAM-1) linuxbios_ram.rom" +makerule coreboot_ram.rom + depends "$(COREBOOT_RAM-1)" + action "cp $(COREBOOT_RAM-1) coreboot_ram.rom" end
-makedefine LINUXBIOS_APC:= +makedefine COREBOOT_APC:=
if CONFIG_AP_CODE_IN_CAR #for ap code in cache
- makerule linuxbios_apc.a + makerule coreboot_apc.a depends "apc_auto.o" - action "rm -f linuxbios_apc.a" - action "ar cr linuxbios_apc.a apc_auto.o" + action "rm -f coreboot_apc.a" + action "ar cr coreboot_apc.a apc_auto.o" end
- makerule linuxbios_apc.o - depends "linuxbios_apc.a c_start.o $(LIBGCC_FILE_NAME)" - action "$(CC) -nostdlib -r -o $@ c_start.o linuxbios_apc.a $(LIBGCC_FILE_NAME)" + makerule coreboot_apc.o + depends "coreboot_apc.a c_start.o $(LIBGCC_FILE_NAME)" + action "$(CC) -nostdlib -r -o $@ c_start.o coreboot_apc.a $(LIBGCC_FILE_NAME)" end
- makerule linuxbios_apc - depends "linuxbios_apc.o $(TOP)/src/config/linuxbios_apc.ld ldoptions" - action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_apc.ld linuxbios_apc.o" - action "$(CROSS_COMPILE)nm -n linuxbios_apc | sort > linuxbios_apc.map" + makerule coreboot_apc + depends "coreboot_apc.o $(TOP)/src/config/linuxbios_apc.ld ldoptions" + action "$(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_apc.ld coreboot_apc.o" + action "$(CROSS_COMPILE)nm -n coreboot_apc | sort > coreboot_apc.map" end
## - ## By default compress the part of linuxbios that runs from cache as ram + ## By default compress the part of coreboot that runs from cache as ram ## - makedefine LINUXBIOS_APC-$(CONFIG_COMPRESS):=linuxbios_apc.nrv2b - makedefine LINUXBIOS_APC-$(CONFIG_UNCOMPRESSED):=linuxbios_apc.bin + makedefine COREBOOT_APC-$(CONFIG_COMPRESS):=coreboot_apc.nrv2b + makedefine COREBOOT_APC-$(CONFIG_UNCOMPRESSED):=coreboot_apc.bin
- makerule linuxbios_apc.bin - depends "linuxbios_apc" + makerule coreboot_apc.bin + depends "coreboot_apc" action "$(OBJCOPY) -O binary $< $@" end
- makerule linuxbios_apc.nrv2b - depends "linuxbios_apc.bin nrv2b" + makerule coreboot_apc.nrv2b + depends "coreboot_apc.bin nrv2b" action "./nrv2b e $< $@" end
- makerule linuxbios_apc.rom - depends "$(LINUXBIOS_APC-1)" - action "cp $(LINUXBIOS_APC-1) linuxbios_apc.rom" + makerule coreboot_apc.rom + depends "$(COREBOOT_APC-1)" + action "cp $(COREBOOT_APC-1) coreboot_apc.rom" end
- makedefine LINUXBIOS_APC:=linuxbios_apc.rom + makedefine COREBOOT_APC:=coreboot_apc.rom
end
-makedefine LINUXBIOS_RAM_ROM:=linuxbios_ram.rom +makedefine COREBOOT_RAM_ROM:=coreboot_ram.rom
-makerule linuxbios - depends "crt0.o $(INIT-OBJECTS) $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld" +makerule coreboot + depends "crt0.o $(INIT-OBJECTS) $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld" action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)" - action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map" + action "$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map" end
#makerule crt0.S @@ -158,14 +158,14 @@ depends "$(SOURCES)" action "ctags $(SOURCES)" end -makerule LinuxBIOSDoc.config - depends "$(TOP)/src/config/LinuxBIOSDoc.config" - action "cat $(TOP)/src/config/LinuxBIOSDoc.config > LinuxBIOSDoc.config" - action "echo 'INPUT=$(SOURCES)' >> LinuxBIOSDoc.config" +makerule corebootDoc.config + depends "$(TOP)/src/config/corebootDoc.config" + action "cat $(TOP)/src/config/corebootDoc.config > corebootDoc.config" + action "echo 'INPUT=$(SOURCES)' >> corebootDoc.config" end makerule documentation - depends "LinuxBIOSDoc.config" - action "doxygen LinuxBIOSDoc.config" + depends "corebootDoc.config" + action "doxygen corebootDoc.config" end
makerule ./romcc @@ -204,12 +204,12 @@ end
makerule clean - action "rm -f linuxbios.* *~" - action "rm -f linuxbios" + action "rm -f coreboot.* *~" + action "rm -f coreboot" action "rm -f ldscript.ld" action "rm -f a.out *.s *.l *.o *.E *.inc" action "rm -f TAGS tags romcc*" - action "rm -f docipl buildrom* chips.c *chip.c linuxbios_apc* linuxbios_ram* linuxbios_pay*" + action "rm -f docipl buildrom* chips.c *chip.c coreboot_apc* coreboot_ram* coreboot_pay*" action "rm -f build_opt_tbl* nrv2b* option_table.c crt0.S" end
Modified: trunk/coreboot-v2/src/config/LinuxBIOSDoc.config =================================================================== --- trunk/coreboot-v2/src/config/LinuxBIOSDoc.config 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/config/LinuxBIOSDoc.config 2008-01-18 15:08:58 UTC (rev 3053) @@ -3,7 +3,7 @@ #--------------------------------------------------------------------------- # Project related configuration options #--------------------------------------------------------------------------- -PROJECT_NAME = LinuxBIOS +PROJECT_NAME = coreboot PROJECT_NUMBER = OUTPUT_DIRECTORY = . CREATE_SUBDIRS = NO
Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/config/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ####################################################### # -# Main options file for LinuxBIOS +# Main options file for coreboot # # Each option used by a part must be defined in # this file. The format for options is: @@ -96,62 +96,62 @@ export always comment "Objcopy command" end -define LINUXBIOS_VERSION +define COREBOOT_VERSION default "2.0.0" export always format ""%s"" - comment "LinuxBIOS version" + comment "coreboot version" end -define LINUXBIOS_EXTRA_VERSION +define COREBOOT_EXTRA_VERSION default "" export used format ""%s"" - comment "LinuxBIOS extra version" + comment "coreboot extra version" end -define LINUXBIOS_BUILD +define COREBOOT_BUILD default "$(shell date)" export always format ""%s"" comment "Build date" end -define LINUXBIOS_COMPILE_TIME +define COREBOOT_COMPILE_TIME default "$(shell date +%T)" export always format ""%s"" comment "Build time" end -define LINUXBIOS_COMPILE_BY +define COREBOOT_COMPILE_BY default "$(shell whoami)" export always format ""%s"" comment "Who build this image" end -define LINUXBIOS_COMPILE_HOST +define COREBOOT_COMPILE_HOST default "$(shell hostname)" export always format ""%s"" comment "Build host" end
-define LINUXBIOS_COMPILE_DOMAIN +define COREBOOT_COMPILE_DOMAIN default "$(shell dnsdomainname)" export always format ""%s"" comment "Build domain name" end -define LINUXBIOS_COMPILER +define COREBOOT_COMPILER default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -n 1)" export always format ""%s"" comment "Build compiler" end -define LINUXBIOS_LINKER +define COREBOOT_LINKER default "$(shell $(CC) -Wl,--version 2>&1 | grep version | tail -n 1)" export always format ""%s"" comment "Build linker" end -define LINUXBIOS_ASSEMBLER +define COREBOOT_ASSEMBLER default "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )" export always format ""%s"" @@ -242,13 +242,13 @@ default {PAYLOAD_SIZE} format "0x%x" export always - comment "Base address of LinuxBIOS in ROM" + comment "Base address of coreboot in ROM" end define _ROMSTART default none format "0x%x" export used - comment "Start address of LinuxBIOS in ROM" + comment "Start address of coreboot in ROM" end define _RESET default {_ROMBASE} @@ -278,13 +278,13 @@ default none format "0x%x" export always - comment "Base address of LinuxBIOS in RAM" + comment "Base address of coreboot in RAM" end define _RAMSTART default none format "0x%x" export used - comment "Start address of LinuxBIOS in RAM" + comment "Start address of coreboot in RAM" end define USE_DCACHE_RAM default 0 @@ -317,7 +317,7 @@ define CONFIG_AP_CODE_IN_CAR default 0 export always - comment "will copy linuxbios_apc to AP cache ane execute in AP" + comment "will copy coreboot_apc to AP cache ane execute in AP" end define MEM_TRAIN_SEQ default 0 @@ -333,13 +333,13 @@ default 0 format "0x%x" export used - comment "Start address of area to cache during LinuxBIOS execution directly from ROM" + comment "Start address of area to cache during coreboot execution directly from ROM" end define XIP_ROM_SIZE default 0 format "0x%x" export used - comment "Size of area to cache during LinuxBIOS execution directly from ROM" + comment "Size of area to cache during coreboot execution directly from ROM" end define CONFIG_COMPRESS default 1 @@ -377,13 +377,13 @@ default 49 format "%d" export always - comment "First CMOS byte to use for LinuxBIOS options" + comment "First CMOS byte to use for coreboot options" end define LB_CKS_RANGE_END default 125 format "%d" export always - comment "Last CMOS byte to use for LinuxBIOS options" + comment "Last CMOS byte to use for coreboot options" end define LB_CKS_LOC default 126
Modified: trunk/coreboot-v2/src/config/doxyscript.base =================================================================== --- trunk/coreboot-v2/src/config/doxyscript.base 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/config/doxyscript.base 2008-01-18 15:08:58 UTC (rev 3053) @@ -16,7 +16,7 @@ # The PROJECT_NAME tag is a single word (or a sequence of words surrounded # by quotes) that should identify the project.
-PROJECT_NAME = "LinuxBIOS" +PROJECT_NAME = "coreboot"
# The PROJECT_NUMBER tag can be used to enter a project or revision number. # This could be handy for archiving the generated documentation or
Modified: trunk/coreboot-v2/src/config/linuxbios_apc.ld =================================================================== --- trunk/coreboot-v2/src/config/linuxbios_apc.ld 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/config/linuxbios_apc.ld 2008-01-18 15:08:58 UTC (rev 3053) @@ -15,7 +15,7 @@ /* * Written by Johan Rydberg, based on work by Daniel Kahlin. * Rewritten by Eric Biederman - * 2005.12 yhlu add linuxbios_ram cross the vga font buffer handling + * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling * 2006.05 yhlu tailed it to use it for AP code in cache */ /* @@ -85,12 +85,12 @@ } _eheap = .; /* The ram segment - * This is all address of the memory resident copy of linuxBIOS. + * This is all address of the memory resident copy of coreboot. */ _ram_seg = _text; _eram_seg = _eheap;
- _bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "linuxbios_apc is too big"); + _bogus = ASSERT( ( _eram_seg <= ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big");
/DISCARD/ : { *(.comment)
Modified: trunk/coreboot-v2/src/config/linuxbios_ram.ld =================================================================== --- trunk/coreboot-v2/src/config/linuxbios_ram.ld 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/config/linuxbios_ram.ld 2008-01-18 15:08:58 UTC (rev 3053) @@ -15,7 +15,7 @@ /* * Written by Johan Rydberg, based on work by Daniel Kahlin. * Rewritten by Eric Biederman - * 2005.12 yhlu add linuxbios_ram cross the vga font buffer handling + * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling */ /* * We use ELF as output format. So that we can @@ -57,7 +57,7 @@ /* * kevinh/Ispiri - Added an align, because the objcopy tool * incorrectly converts sections that are not long word aligned. - * This breaksthe linuxbios.strip target. + * This breaks the coreboot.strip target. */ . = ALIGN(4);
@@ -104,7 +104,7 @@ } _eheap = .; /* The ram segment - * This is all address of the memory resident copy of linuxBIOS. + * This is all address of the memory resident copy of coreboot. */ _ram_seg = _text; _eram_seg = _eheap;
Modified: trunk/coreboot-v2/src/console/btext_console.c =================================================================== --- trunk/coreboot-v2/src/console/btext_console.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/console/btext_console.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -3,7 +3,7 @@ * * Benjamin Herrenschmidt benh@kernel.crashing.org * - * move to LinuxBIOS by LYH yhlu@tyan.com + * move to coreboot by LYH yhlu@tyan.com */
#if 0
Modified: trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -23,7 +23,7 @@ uint8_t *src, *dst; unsigned long ilen, olen;
- print_debug("Copying LinuxBIOS to RAM.\r\n"); + print_debug("Copying coreboot to RAM.\r\n");
#if !CONFIG_COMPRESS __asm__ volatile ( @@ -55,7 +55,7 @@
print_debug_cp_run("linxbios_ram.bin length = ", olen);
- print_debug("Jumping to LinuxBIOS.\r\n"); + print_debug("Jumping to coreboot.\r\n");
__asm__ volatile ( "xorl %ebp, %ebp\n\t" /* cpu_reset for hardwaremain dummy */ @@ -73,7 +73,7 @@ uint8_t *src, *dst; unsigned long ilen, olen;
-// print_debug("Copying LinuxBIOS AP code to CAR.\r\n"); +// print_debug("Copying coreboot AP code to CAR.\r\n");
#if !CONFIG_COMPRESS __asm__ volatile ( @@ -105,7 +105,7 @@
// print_debug_cp_run("linxbios_apc.bin length = ", olen);
-// print_debug("Jumping to LinuxBIOS AP code in CAR.\r\n"); +// print_debug("Jumping to coreboot AP code in CAR.\r\n");
__asm__ volatile ( "movl %0, %%ebp\n\t" /* cpu_reset for hardwaremain dummy */
Modified: trunk/coreboot-v2/src/cpu/amd/car/disable_cache_as_ram.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/disable_cache_as_ram.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/amd/car/disable_cache_as_ram.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -21,7 +21,7 @@ "wrmsr\n\t" #endif
- /* disable fixed mtrr from now on, it will be enabled by linuxbios_ram again*/ + /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/ "movl $0xC0010010, %ecx\n\t" // "movl $SYSCFG_MSR, %ecx\n\t" "rdmsr\n\t"
Modified: trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -104,7 +104,7 @@ // wait for ap memory to trained // wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c #endif - /*copy and execute linuxbios_ram */ + /*copy and execute coreboot_ram */ copy_and_run(); /* We will not return */
Modified: trunk/coreboot-v2/src/cpu/amd/model_gx2/vsmsetup.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_gx2/vsmsetup.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/amd/model_gx2/vsmsetup.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ /* what a mess this uncompress thing is. I am not at all happy about how this * was done, but can't fix it yet. RGM */ -#warning "Fix the uncompress once linuxbios knows how to do it" +#warning "Fix the uncompress once coreboot knows how to do it" #include "../lib/nrv2b.c"
/* vsmsetup.c derived from vgabios.c. Derived from: */ @@ -71,7 +71,7 @@ *--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used - without reliance on other parts of core Linuxbios + without reliance on other parts of core coreboot (C) 2005 Nick.Barker9@btinternet.com
Used initially for epia-m where there are problems getting the bios @@ -320,10 +320,10 @@ // that simplifies a lot of things ... // we'll just push all the registers on the stack as longwords, // and pop to protected mode. -// second, since this only ever runs as part of linuxbios, +// second, since this only ever runs as part of coreboot, // we know all the segment register values -- so we don't save any. // keep the handler that calls things small. It can do a call to -// more complex code in linuxbios itself. This helps a lot as we don't +// more complex code in coreboot itself. This helps a lot as we don't // have to do address fixup in this little stub, and calls are absolute // so the handler is relocatable. void handler(void)
Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc 2008-01-18 15:08:58 UTC (rev 3053) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#define LX_STACK_BASE DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */ +#define LX_STACK_BASE DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ #define LX_STACK_END LX_STACK_BASE+(DCACHE_RAM_SIZE-1)
#define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */ @@ -213,7 +213,7 @@
cld /* clear direction flag */
- /* copy linuxBIOS from it's initial load location to + /* copy coreboot from it's initial load location to * the location it is compiled to run at. * Normally this is copying from FLASH ROM to RAM. */ @@ -363,8 +363,8 @@
#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) .section ".rom.data" -str_copying_to_ram: .string "Copying LinuxBIOS to ram.\r\n" -str_pre_main: .string "Jumping to LinuxBIOS.\r\n" +str_copying_to_ram: .string "Copying coreboot to ram.\r\n" +str_pre_main: .string "Jumping to coreboot.\r\n" .previous
#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/vsmsetup.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_lx/vsmsetup.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/amd/model_lx/vsmsetup.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -75,7 +75,7 @@ *--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used - without reliance on other parts of core Linuxbios + without reliance on other parts of core coreboot (C) 2005 Nick.Barker9@btinternet.com
Used initially for epia-m where there are problems getting the bios @@ -341,10 +341,10 @@ // that simplifies a lot of things ... // we'll just push all the registers on the stack as longwords, // and pop to protected mode. -// second, since this only ever runs as part of linuxbios, +// second, since this only ever runs as part of coreboot, // we know all the segment register values -- so we don't save any. // keep the handler that calls things small. It can do a call to -// more complex code in linuxbios itself. This helps a lot as we don't +// more complex code in coreboot itself. This helps a lot as we don't // have to do address fixup in this little stub, and calls are absolute // so the handler is relocatable. void handler(void)
Modified: trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -157,7 +157,7 @@ /* these are ENDING addresses, not sizes. * if there is memory in this slot, then reg will be > rambits. * So we just take the max, that gives us total. - * We take the highest one to cover for once and future linuxbios + * We take the highest one to cover for once and future coreboot * bugs. We warn about bugs. */ if (reg > rambits)
Modified: trunk/coreboot-v2/src/cpu/emulation/qemu-i386/northbridge.c =================================================================== --- trunk/coreboot-v2/src/cpu/emulation/qemu-i386/northbridge.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/emulation/qemu-i386/northbridge.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -86,7 +86,7 @@ /* these are ENDING addresses, not sizes. * if there is memory in this slot, then reg will be > rambits. * So we just take the max, that gives us total. - * We take the highest one to cover for once and future linuxbios + * We take the highest one to cover for once and future coreboot * bugs. We warn about bugs. */ if (reg > rambits)
Modified: trunk/coreboot-v2/src/cpu/ppc/mpc74xx/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/ppc/mpc74xx/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/ppc/mpc74xx/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ ## Use cache ram for initial setup ## default USE_DCACHE_RAM=1 -## Set dcache ram above linuxbios image +## Set dcache ram above coreboot image default DCACHE_RAM_BASE=_RAMBASE+0x100000 ## Dcache size is 32Kb default DCACHE_RAM_SIZE=0x8000
Modified: trunk/coreboot-v2/src/cpu/ppc/mpc74xx/mpc74xx.inc =================================================================== --- trunk/coreboot-v2/src/cpu/ppc/mpc74xx/mpc74xx.inc 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/ppc/mpc74xx/mpc74xx.inc 2008-01-18 15:08:58 UTC (rev 3053) @@ -19,7 +19,7 @@
/* * The aim of this code is to bring the machine from power-on to the point - * where we can jump to the the main LinuxBIOS entry point hardwaremain() + * where we can jump to the the main coreboot entry point hardwaremain() * which is written in C. * * At power-on, we have no RAM, a memory-mapped I/O space, and we are executing @@ -79,7 +79,7 @@ isync
/* - * Clear segment registers (LinuxBIOS doesn't use these) + * Clear segment registers (coreboot doesn't use these) */ mtsr 0, r0 isync
Modified: trunk/coreboot-v2/src/cpu/ppc/ppc4xx/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/ppc/ppc4xx/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/ppc/ppc4xx/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ ## PPC4XX always uses cache ram for initial setup ## default USE_DCACHE_RAM=1 -## Set dcache ram above linuxbios image +## Set dcache ram above coreboot image default DCACHE_RAM_BASE=_RAMBASE+0x100000 ## Dcache size is 16Kb default DCACHE_RAM_SIZE=16384
Modified: trunk/coreboot-v2/src/cpu/ppc/ppc7xx/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/ppc/ppc7xx/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/ppc/ppc7xx/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ ## PPC7XX always uses cache ram for initial setup ## default USE_DCACHE_RAM=1 -## Set dcache ram above linuxbios image +## Set dcache ram above coreboot image default DCACHE_RAM_BASE=_RAMBASE+0x100000 ## Dcache size is 16Kb default DCACHE_RAM_SIZE=16384
Modified: trunk/coreboot-v2/src/cpu/ppc/ppc7xx/ppc7xx.inc =================================================================== --- trunk/coreboot-v2/src/cpu/ppc/ppc7xx/ppc7xx.inc 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/ppc/ppc7xx/ppc7xx.inc 2008-01-18 15:08:58 UTC (rev 3053) @@ -19,7 +19,7 @@
/* * The aim of this code is to bring the machine from power-on to the point - * where we can jump to the the main LinuxBIOS entry point hardwaremain() + * where we can jump to the the main coreboot entry point hardwaremain() * which is written in C. * * At power-on, we have no RAM, a memory-mapped I/O space, and we are executing @@ -72,7 +72,7 @@ isync
/* - * Clear segment registers (LinuxBIOS doesn't use these) + * Clear segment registers (coreboot doesn't use these) */ li r3, 15 1: mtsrin r3, r0
Modified: trunk/coreboot-v2/src/cpu/x86/32bit/entry32.inc =================================================================== --- trunk/coreboot-v2/src/cpu/x86/32bit/entry32.inc 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/x86/32bit/entry32.inc 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,4 +1,4 @@ -/* For starting linuxBIOS in protected mode */ +/* For starting coreboot in protected mode */
#include <arch/rom_segs.h>
@@ -8,8 +8,8 @@ .align 4 .globl gdtptr
- /* This is the gdt for ROMCC/ASM part of LinuxBIOS. - * It is different from the gdt in GCC part of LinuxBIOS + /* This is the gdt for ROMCC/ASM part of coreboot. + * It is different from the gdt in GCC part of coreboot * which is defined in c_start.S */ gdt: gdtptr:
Modified: trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -15,7 +15,7 @@ unsigned long dst_len; unsigned long ilen, olen;
- print_debug("Copying LinuxBIOS to RAM.\r\n"); + print_debug("Copying coreboot to RAM.\r\n");
#if !CONFIG_COMPRESS __asm__ volatile ( @@ -53,7 +53,7 @@ #else print_debug("linxbios_ram.bin length = "); print_debug_hex32(olen); print_debug("\r\n"); #endif - print_debug("Jumping to LinuxBIOS.\r\n"); + print_debug("Jumping to coreboot.\r\n");
if(cpu_reset == 1 ) { __asm__ volatile (
Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,5 +1,5 @@ /* - 2005.12 yhlu add linuxbios_ram cross the vga font buffer handling + 2005.12 yhlu add coreboot_ram cross the vga font buffer handling 2005.12 yhlu add _RAMBASE above 1M support for SMP */
@@ -191,7 +191,7 @@ return 1; }
-/* Number of cpus that are currently running in linuxbios */ +/* Number of cpus that are currently running in coreboot */ static atomic_t active_cpus = ATOMIC_INIT(1);
/* start_cpu_lock covers last_cpu_index and secondary_stack.
Modified: trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/cpu/x86/pae/pgtbl.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,5 +1,5 @@ /* - 2005.12 yhlu add linuxbios_ram cross the vga font buffer handling + 2005.12 yhlu add coreboot_ram cross the vga font buffer handling */
#include <console/console.h>
Modified: trunk/coreboot-v2/src/devices/emulator/x86emu/sys.c =================================================================== --- trunk/coreboot-v2/src/devices/emulator/x86emu/sys.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/devices/emulator/x86emu/sys.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -45,7 +45,7 @@ #include <x86emu/regs.h> #include "debug.h" #include "prim_ops.h" -#ifdef LINUXBIOS_VERSION +#ifdef COREBOOT_VERSION #include "arch/io.h" #else #include <sys/io.h>
Modified: trunk/coreboot-v2/src/drivers/ati/ragexl/xlinit.c =================================================================== --- trunk/coreboot-v2/src/drivers/ati/ragexl/xlinit.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/drivers/ati/ragexl/xlinit.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -7,7 +7,7 @@ * stevel@mvista.com or source@mvista.com * Copyright (C) 2004 Tyan Computer. * Auther: Yinghai Lu yhlu@tyan.com - * move to LinuxBIOS + * move to coreboot * This code is distributed without warranty under the GPL v2 (see COPYING) * */ #include <delay.h>
Modified: trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c =================================================================== --- trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -24,8 +24,8 @@ in your MB targets Config.lb, afer romimage "normal" 3. create you vgabios.bin under normal bios and put that in dir that targets Config residues. # dd if=/dev/mem of=atix.rom skip=1536 count=96 - 4. after build linuxbios.rom - # cat ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > linuxbios.rom + 4. after build coreboot.rom + # cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > coreboot.rom or use nsxv to build you image # time ./nsxv s2850
@@ -52,8 +52,8 @@ tail -n 15 "$LBROOT/x_m.txt" exit fi -cat ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > "$LBROOT/rom/"$MBMODEL"_linuxbios.rom" -cp -f "$LBROOT/rom/"$MBMODEL"_linuxbios.rom" /home/yhlu/ +cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > "$LBROOT/rom/"$MBMODEL"_coreboot.rom" +cp -f "$LBROOT/rom/"$MBMODEL"_coreboot.rom" /home/yhlu/
date
Modified: trunk/coreboot-v2/src/include/boot/elf.h =================================================================== --- trunk/coreboot-v2/src/include/boot/elf.h 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/include/boot/elf.h 2008-01-18 15:08:58 UTC (rev 3053) @@ -394,7 +394,7 @@ struct lb_memory; extern int elfboot(struct lb_memory *mem);
-#define FIRMWARE_TYPE "LinuxBIOS" +#define FIRMWARE_TYPE "coreboot" #define BOOTLOADER "elfboot" #define BOOTLOADER_VERSION "1.3"
Modified: trunk/coreboot-v2/src/include/boot/linuxbios_tables.h =================================================================== --- trunk/coreboot-v2/src/include/boot/linuxbios_tables.h 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/include/boot/linuxbios_tables.h 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,9 +1,9 @@ -#ifndef LINUXBIOS_TABLES_H -#define LINUXBIOS_TABLES_H +#ifndef COREBOOT_TABLES_H +#define COREBOOT_TABLES_H
#include <stdint.h>
-/* The linuxbios table information is for conveying information +/* The coreboot table information is for conveying information * from the firmware to the loaded OS image. Primarily this * is expected to be information that cannot be discovered by * other means, such as quering the hardware directly. @@ -31,12 +31,12 @@ * table entries and be backwards compatible, but it is not required. */
-/* Since LinuxBIOS is usually compiled 32bit, gcc will align 64bit - * types to 32bit boundaries. If the LinuxBIOS table is dumped on a +/* Since coreboot is usually compiled 32bit, gcc will align 64bit + * types to 32bit boundaries. If the coreboot table is dumped on a * 64bit system, a uint64_t would be aligned to 64bit boundaries, * breaking the table format. * - * lb_uint64 will keep 64bit LinuxBIOS table values aligned to 32bit + * lb_uint64 will keep 64bit coreboot table values aligned to 32bit * to ensure compatibility. They can be accessed with the two functions * below: unpack_lb64() and pack_lb64() * @@ -213,4 +213,4 @@
-#endif /* LINUXBIOS_TABLES_H */ +#endif /* COREBOOT_TABLES_H */
Modified: trunk/coreboot-v2/src/include/console/btext.h =================================================================== --- trunk/coreboot-v2/src/include/console/btext.h 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/include/console/btext.h 2008-01-18 15:08:58 UTC (rev 3053) @@ -4,7 +4,7 @@ * * Written by Benjamin Herrenschmidt. * - * Move to LinuxBIOS by LYH yhlu@tyan.com + * Move to coreboot by LYH yhlu@tyan.com * */
Modified: trunk/coreboot-v2/src/include/device/pci_ids.h =================================================================== --- trunk/coreboot-v2/src/include/device/pci_ids.h 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/include/device/pci_ids.h 2008-01-18 15:08:58 UTC (rev 3053) @@ -2507,7 +2507,7 @@ #define PCI_DEVICE_ID_SIS_SIS968_PCIE 0x000a /* D6F0,D7F0 */ #define PCI_DEVICE_ID_SIS_SIS968_HD_AUDIO 0x7502 /* DfF0 */
-/* OLD USAGE FOR LINUXBIOS */ +/* OLD USAGE FOR COREBOOT */ #define PCI_VENDOR_ID_ACER 0x10b9 #define PCI_DEVICE_ID_ACER_M1535D 0x1533
Modified: trunk/coreboot-v2/src/include/version.h =================================================================== --- trunk/coreboot-v2/src/include/version.h 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/include/version.h 2008-01-18 15:08:58 UTC (rev 3053) @@ -5,18 +5,18 @@ extern const char mainboard_vendor[]; extern const char mainboard_part_number[];
-/* LinuxBIOS Version */ -extern const char linuxbios_version[]; -extern const char linuxbios_extra_version[]; -extern const char linuxbios_build[]; +/* coreboot Version */ +extern const char coreboot_version[]; +extern const char coreboot_extra_version[]; +extern const char coreboot_build[];
-/* When LinuxBIOS was compiled */ -extern const char linuxbios_compile_time[]; -extern const char linuxbios_compile_by[]; -extern const char linuxbios_compile_host[]; -extern const char linuxbios_compile_domain[]; -extern const char linuxbios_compiler[]; -extern const char linuxbios_linker[]; -extern const char linuxbios_assembler[]; +/* When coreboot was compiled */ +extern const char coreboot_compile_time[]; +extern const char coreboot_compile_by[]; +extern const char coreboot_compile_host[]; +extern const char coreboot_compile_domain[]; +extern const char coreboot_compiler[]; +extern const char coreboot_linker[]; +extern const char coreboot_assembler[];
#endif /* VERSION_H */
Modified: trunk/coreboot-v2/src/include/x86emu/x86emu.h =================================================================== --- trunk/coreboot-v2/src/include/x86emu/x86emu.h 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/include/x86emu/x86emu.h 2008-01-18 15:08:58 UTC (rev 3053) @@ -43,7 +43,7 @@ #define __X86EMU_X86EMU_H
/* FIXME: undefine printk for the moment */ -#ifdef LINUXBIOS_VERSION +#ifdef COREBOOT_VERSION #include "console/console.h" #define printk printk_debug #else
Modified: trunk/coreboot-v2/src/lib/lzma.c =================================================================== --- trunk/coreboot-v2/src/lib/lzma.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/lib/lzma.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ /*
-LinuxBIOS interface to memory-saving variant of LZMA decoder +Coreboot interface to memory-saving variant of LZMA decoder (C)opyright 2006 Carl-Daniel Hailfinger Released under the GNU GPL
Modified: trunk/coreboot-v2/src/lib/usbdebug_direct.c =================================================================== --- trunk/coreboot-v2/src/lib/usbdebug_direct.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/lib/usbdebug_direct.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -5,7 +5,7 @@ * modify it under the terms of the GNU General Public License version * 2 as published by the Free Software Foundation. * - * 2006.12.10 yhlu moved it to LinuxBIOS and use struct instead + * 2006.12.10 yhlu moved it to corbeoot and use struct instead */ #ifndef __ROMCC__ #include <console/console.h>
Modified: trunk/coreboot-v2/src/lib/version.c =================================================================== --- trunk/coreboot-v2/src/lib/version.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/lib/version.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -7,52 +7,52 @@ #error MAINBOARD_PART_NUMBER not defined #endif
-#ifndef LINUXBIOS_VERSION -#error LINUXBIOS_VERSION not defined +#ifndef COREBOOT_VERSION +#error COREBOOT_VERSION not defined #endif -#ifndef LINUXBIOS_BUILD -#error LINUXBIOS_BUILD not defined +#ifndef COREBOOT_BUILD +#error COREBOOT_BUILD not defined #endif
-#ifndef LINUXBIOS_COMPILE_TIME -#error LINUXBIOS_COMPILE_TIME not defined +#ifndef COREBOOT_COMPILE_TIME +#error COREBOOT_COMPILE_TIME not defined #endif -#ifndef LINUXBIOS_COMPILE_BY -#error LINUXBIOS_COMPILE_BY not defined +#ifndef COREBOOT_COMPILE_BY +#error COREBOOT_COMPILE_BY not defined #endif -#ifndef LINUXBIOS_COMPILE_HOST -#error LINUXBIOS_COMPILE_HOST not defined +#ifndef COREBOOT_COMPILE_HOST +#error COREBOOT_COMPILE_HOST not defined #endif
-#ifndef LINUXBIOS_COMPILER -#error LINUXBIOS_COMPILER not defined +#ifndef COREBOOT_COMPILER +#error COREBOOT_COMPILER not defined #endif -#ifndef LINUXBIOS_LINKER -#error LINUXBIOS_LINKER not defined +#ifndef COREBOOT_LINKER +#error COREBOOT_LINKER not defined #endif -#ifndef LINUXBIOS_ASSEMBLER -#error LINUXBIOS_ASSEMBLER not defined +#ifndef COREBOOT_ASSEMBLER +#error COREBOOT_ASSEMBLER not defined #endif
-#ifndef LINUXBIOS_EXTRA_VERSION -#define LINUXBIOS_EXTRA_VERSION "" +#ifndef COREBOOT_EXTRA_VERSION +#define COREBOOT_EXTRA_VERSION "" #endif
const char mainboard_vendor[] = MAINBOARD_VENDOR; const char mainboard_part_number[] = MAINBOARD_PART_NUMBER;
-const char linuxbios_version[] = LINUXBIOS_VERSION; -const char linuxbios_extra_version[] = LINUXBIOS_EXTRA_VERSION; -const char linuxbios_build[] = LINUXBIOS_BUILD; +const char coreboot_version[] = COREBOOT_VERSION; +const char coreboot_extra_version[] = COREBOOT_EXTRA_VERSION; +const char coreboot_build[] = COREBOOT_BUILD;
-const char linuxbios_compile_time[] = LINUXBIOS_COMPILE_TIME; -const char linuxbios_compile_by[] = LINUXBIOS_COMPILE_BY; -const char linuxbios_compile_host[] = LINUXBIOS_COMPILE_HOST; -const char linuxbios_compile_domain[] = LINUXBIOS_COMPILE_DOMAIN; -const char linuxbios_compiler[] = LINUXBIOS_COMPILER; -const char linuxbios_linker[] = LINUXBIOS_LINKER; -const char linuxbios_assembler[] = LINUXBIOS_ASSEMBLER; +const char coreboot_compile_time[] = COREBOOT_COMPILE_TIME; +const char coreboot_compile_by[] = COREBOOT_COMPILE_BY; +const char coreboot_compile_host[] = COREBOOT_COMPILE_HOST; +const char coreboot_compile_domain[] = COREBOOT_COMPILE_DOMAIN; +const char coreboot_compiler[] = COREBOOT_COMPILER; +const char coreboot_linker[] = COREBOOT_LINKER; +const char coreboot_assembler[] = COREBOOT_ASSEMBLER;
Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE
Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE
Modified: trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -145,7 +145,7 @@
end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ##
mainboardinit cpu/x86/16bit/entry16.inc @@ -163,7 +163,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -193,7 +193,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/agami/aruma/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/agami/aruma/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/agami/aruma/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -37,7 +37,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CC uses HOSTCC @@ -140,7 +140,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -196,10 +196,10 @@
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -218,7 +218,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -262,7 +262,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately @@ -275,7 +275,7 @@ ## SPEW 9 Way too many details
-## These values can be overwritten by LinuxBIOSv2/targets/agami/aruma/Config.lb +## These values can be overwritten by corebootv2/targets/agami/aruma/Config.lb ## Request this level of debugging output default DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging
Modified: trunk/coreboot-v2/src/mainboard/agami/aruma/acpi_tables_static.c =================================================================== --- trunk/coreboot-v2/src/mainboard/agami/aruma/acpi_tables_static.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/agami/aruma/acpi_tables_static.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -83,7 +83,7 @@
/* The next two tables are used by our DSDT and are freely defined * here. This construct is used because the bus numbers containing - * the 8131 bridges may vary so that we need to pass LinuxBIOS + * the 8131 bridges may vary so that we need to pass coreboot * knowledge into the DSDT */ typedef struct lnxc_busses { @@ -96,7 +96,7 @@ acpi_lnxb_busses_t busses[5]; } acpi_lnxb_t;
-/* special linuxbios acpi table */ +/* special coreboot acpi table */ void acpi_create_lnxb(acpi_lnxb_t *lnxb) { device_t dev;
Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,19 +12,19 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -62,7 +62,7 @@
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -70,7 +70,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -90,7 +90,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -70,7 +70,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -92,10 +92,10 @@ default HAVE_OPTION_TABLE=0
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
@@ -158,7 +158,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,19 +12,19 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -64,7 +64,7 @@
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -72,7 +72,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -92,7 +92,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -70,7 +70,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -92,10 +92,10 @@ default HAVE_OPTION_TABLE=0
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
@@ -158,7 +158,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -70,7 +70,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -78,7 +78,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -98,7 +98,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -60,7 +60,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -82,10 +82,10 @@ default HAVE_OPTION_TABLE=0
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
@@ -141,7 +141,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE @@ -17,18 +17,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -154,7 +154,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ##
if HAVE_FAILOVER_BOOT @@ -181,7 +181,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -215,7 +215,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -40,7 +40,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -122,7 +122,7 @@ default HAVE_FAILOVER_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -149,7 +149,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -237,10 +237,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -259,7 +259,7 @@ default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00100000
@@ -309,7 +309,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,7 +1,7 @@ At this time, For acpi support We got -1. support AMK K8 SRAT --- dynamically (LinuxBIOS run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c) -2. support MADT ---- dynamically (LinuxBIOS run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c) -3. support DSDT ---- dynamically (Compile time, LinuxBIOS run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{dx/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c) +1. support AMK K8 SRAT --- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c) +2. support MADT ---- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c) +3. support DSDT ---- dynamically (Compile time, coreboot run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{dx/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c) 4. Chipset support: amd8111, amd8132
The developers need to change for different MB @@ -11,7 +11,7 @@ if there is HT-IO board, may use pci2.asl.... to create ssdt2.c, and ssdt3,c and ssdt4.c, ....ssdt8.c
Change acpi_tables.c - sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents. ---- Actually you don't need to change it, it is LinuxBIOS run-time configurable now. + sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents. ---- Actually you don't need to change it, it is coreboot run-time configurable now. if there is HT-IO board, need to adjust SSDTX_NUM...., and preset pci1234 array. acpi_tables.c will decide to put the SSDT on the RSDT or not according if the HT-IO board is installed
Regarding pci bridge apic and pic
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -19,7 +19,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE @@ -36,18 +36,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -163,7 +163,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ##
if HAVE_FAILOVER_BOOT @@ -190,7 +190,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -225,7 +225,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -59,7 +59,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -147,7 +147,7 @@ default HAVE_FAILOVER_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -174,7 +174,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -261,10 +261,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -283,7 +283,7 @@ default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00200000
@@ -334,7 +334,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -91,7 +91,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -111,7 +111,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -141,7 +141,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -34,7 +34,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -82,7 +82,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -104,7 +104,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -145,10 +145,10 @@
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -167,7 +167,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -216,7 +216,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -60,7 +60,7 @@
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -68,7 +68,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -88,7 +88,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -70,7 +70,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -93,10 +93,10 @@ default HAVE_OPTION_TABLE=0
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
@@ -159,7 +159,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/realmode/vgabios.c =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/realmode/vgabios.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/realmode/vgabios.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -66,7 +66,7 @@ *--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used - without reliance on other parts of core Linuxbios + without reliance on other parts of core coreboot (C) 2005 Nick.Barker9@btinternet.com
Used initially for epia-m where there are problems getting the bios @@ -442,10 +442,10 @@ // that simplifies a lot of things ... // we'll just push all the registers on the stack as longwords, // and pop to protected mode. -// second, since this only ever runs as part of linuxbios, +// second, since this only ever runs as part of coreboot, // we know all the segment register values -- so we don't save any. // keep the handler that calls things small. It can do a call to -// more complex code in linuxbios itself. This helps a lot as we don't +// more complex code in coreboot itself. This helps a lot as we don't // have to do address fixup in this little stub, and calls are absolute // so the handler is relocatable. void handler_vga(void) @@ -921,7 +921,7 @@
pci_dev_init(dev);
- // code to make vga init run in real mode - does work but against the current Linuxbios philosophy + // code to make vga init run in real mode - does work but against the current coreboot philosophy printk_debug("INSTALL REAL-MODE IDT\n"); setup_realmode_idt(); printk_debug("DO THE VGA BIOS\n");
Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -71,7 +71,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -79,7 +79,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -99,7 +99,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -7,7 +7,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -57,7 +57,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -78,10 +78,10 @@ # default HAVE_OPTION_TABLE=0
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 64 * 1024 default FALLBACK_SIZE = 128 * 1024
@@ -137,7 +137,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -23,7 +23,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE @@ -39,18 +39,18 @@ end
## -## Compute the start location and size size of the LinuxBIOS bootloader. +## Compute the start location and size size of the coreboot bootloader. ## default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of LinuxBIOS will start in the boot ROM. +## Compute where this copy of coreboot will start in the boot ROM. ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can be cached to speed up LinuxBIOS +## Compute a range of ROM that can be cached to speed up coreboot ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte) @@ -106,7 +106,7 @@ end
## -## Build our 16 bit and 32 bit LinuxBIOS entry code. +## Build our 16 bit and 32 bit coreboot entry code. ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -130,7 +130,7 @@ end
## -## Build our reset vector (this is where LinuxBIOS is entered). +## Build our reset vector (this is where coreboot is entered). ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -186,7 +186,7 @@
### -### This is the early phase of LinuxBIOS startup. +### This is the early phase of coreboot startup. ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -59,7 +59,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CONFIG_GDB_STUB uses CROSS_COMPILE @@ -127,7 +127,7 @@ default HAVE_FAILOVER_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -149,7 +149,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -223,10 +223,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = (64*1024) #65536
@@ -247,7 +247,7 @@ default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -296,7 +296,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -23,7 +23,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -35,19 +35,19 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -97,7 +97,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ##
if USE_FALLBACK_IMAGE @@ -122,7 +122,7 @@
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ##
if USE_FALLBACK_IMAGE @@ -141,7 +141,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -56,7 +56,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CONFIG_GDB_STUB uses CROSS_COMPILE @@ -121,7 +121,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -143,7 +143,7 @@ default HAVE_OPTION_TABLE=0
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -217,10 +217,10 @@ #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 64 * 1024
## @@ -242,7 +242,7 @@ ##default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -291,7 +291,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE
Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -70,7 +70,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -78,7 +78,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -98,7 +98,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -60,7 +60,7 @@ default HAVE_MP_TABLE = 0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET = 0
@@ -79,10 +79,10 @@ default CONFIG_IDE = 1
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
@@ -138,7 +138,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE
Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE
Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE
Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE
Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/tc320/irq_tables.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/axus/tc320/irq_tables.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -24,7 +24,7 @@ * It was not possible to read back the PIRQ table. There was no BIOS to ask * for it, only a bootloader for an embedded OS. * But with the method described here: - * http://linuxbios.org/Creating_Valid_IRQ_Tables + * http://coreboot.org/Creating_Valid_IRQ_Tables * it was possible to detect the physical IRQ routing on this board. * * This is the physical routing on this board:
Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE
Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE
Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE
Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -72,7 +72,7 @@
end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -88,7 +88,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -112,7 +112,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -36,7 +36,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -89,7 +89,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -111,7 +111,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -168,10 +168,10 @@
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -190,7 +190,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -239,7 +239,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE
Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -5,7 +5,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -17,18 +17,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -75,7 +75,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -83,7 +83,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -103,7 +103,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -34,7 +34,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses _RAMBASE @@ -75,7 +75,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -97,7 +97,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -125,10 +125,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -144,12 +144,12 @@
### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### default FALLBACK_SIZE=131072
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -199,7 +199,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -69,7 +69,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -77,7 +77,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -97,7 +97,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -11,7 +11,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -57,7 +57,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -79,10 +79,10 @@ default HAVE_OPTION_TABLE=1
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## default ROM_SIZE = 512 * 1024 default FALLBACK_SIZE = 0x10000 @@ -14,18 +14,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -71,7 +71,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -79,7 +79,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -99,7 +99,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -12,7 +12,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -70,7 +70,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -87,10 +87,10 @@ default HAVE_OPTION_TABLE=1
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -61,7 +61,7 @@
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -69,7 +69,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -89,7 +89,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -70,7 +70,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -92,10 +92,10 @@ default HAVE_OPTION_TABLE=0
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
@@ -158,7 +158,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -101,7 +101,7 @@ Just wbinvd the stack to clear the cache tags. We don't care where the stack used to be. 2. This file is built as a normal .c -> .o and linked in etc. The stack might be used to return etc. That means we care about what is in the stack. If we are smart we set the CAR stack to the same location - as the rest of LinuxBIOS. If that is the case we can just do a wbinvd. The stack will be written into real + as the rest of coreboot. If that is the case we can just do a wbinvd. The stack will be written into real RAM that is now setup and we continue like nothing happened. If the stack is located somewhere other than where LB would like it, you need to write some code to do a copy from cache to RAM
Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -70,7 +70,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -78,7 +78,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -98,7 +98,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -61,7 +61,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -83,10 +83,10 @@ default HAVE_OPTION_TABLE=0
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
@@ -142,7 +142,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -23,5 +23,5 @@ ## Build the objects we have code for in this directory. ##
-addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a" +addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a" makedefine CFLAGS += -msoft-float
Modified: trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -44,7 +44,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses CROSS_COMPILE uses CC uses HOSTCC @@ -106,7 +106,7 @@ ## Board has fixed size RAM default EMBEDDED_RAM_SIZE=64*1024*1024
-## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM default _RAMBASE=0x00100000
## @@ -133,10 +133,10 @@ ## Exception vectors default _EXCEPTION_VECTORS=_ROMBASE+0x100
-## linuxBIOS ROM start address +## coreboot ROM start address default _ROMSTART=0xfff03000
-## linuxBIOS C code runs at this location in RAM +## coreboot C code runs at this location in RAM default _RAMBASE=0x00100000
### End Options.lb
Modified: trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg =================================================================== --- trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg 2008-01-18 15:08:58 UTC (rev 3053) @@ -62,7 +62,7 @@ [HOST] IP 10.0.1.2 FORMAT ELF -FILE linuxbios.elf +FILE coreboot.elf ;START 0x200000 LOAD MANUAL ;load code MANUAL or AUTO after reset DEBUGPORT 2001
Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-i386/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-i386/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-i386/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## default ROM_SIZE = 256 * 1024 default ROM_SECTION_SIZE = ROM_SIZE @@ -8,18 +8,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -66,7 +66,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -74,7 +74,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds
Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-i386/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-i386/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-i386/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -14,7 +14,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -63,7 +63,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -80,10 +80,10 @@ default HAVE_OPTION_TABLE=1
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-i386/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-i386/mainboard.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-i386/mainboard.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@
static void vga_init(device_t dev) { - /* code to make vga init run in real mode - does work but against the current Linuxbios philosophy */ + /* code to make vga init run in real mode - does work but against the current coreboot philosophy */ printk_debug("INSTALL REAL-MODE IDT\n"); setup_realmode_idt(); printk_debug("DO THE VGA BIOS\n");
Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-i386/vgabios.c =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-i386/vgabios.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-i386/vgabios.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -64,7 +64,7 @@ *--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used - without reliance on other parts of core Linuxbios + without reliance on other parts of core coreboot (C) 2005 Nick.Barker9@btinternet.com
Used initially for epia-m where there are problems getting the bios @@ -398,10 +398,10 @@ // that simplifies a lot of things ... // we'll just push all the registers on the stack as longwords, // and pop to protected mode. -// second, since this only ever runs as part of linuxbios, +// second, since this only ever runs as part of coreboot, // we know all the segment register values -- so we don't save any. // keep the handler that calls things small. It can do a call to -// more complex code in linuxbios itself. This helps a lot as we don't +// more complex code in coreboot itself. This helps a lot as we don't // have to do address fixup in this little stub, and calls are absolute // so the handler is relocatable. void handler(void)
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -23,7 +23,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE @@ -40,18 +40,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -113,7 +113,7 @@
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -141,7 +141,7 @@
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -190,7 +190,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -64,7 +64,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -148,7 +148,7 @@ default HAVE_FAILOVER_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -173,7 +173,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -259,10 +259,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -281,7 +281,7 @@ default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00100000
@@ -333,7 +333,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -21,7 +21,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE @@ -38,18 +38,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -111,7 +111,7 @@
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -139,7 +139,7 @@
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -188,7 +188,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -62,7 +62,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -146,7 +146,7 @@ default HAVE_FAILOVER_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -171,7 +171,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -257,10 +257,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -279,7 +279,7 @@ default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00100000
@@ -331,7 +331,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -92,7 +92,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -112,7 +112,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -142,7 +142,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -32,7 +32,7 @@ uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR uses MAINBOARD -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -71,7 +71,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -93,7 +93,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -129,10 +129,10 @@ #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -151,7 +151,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -195,7 +195,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -92,7 +92,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -112,7 +112,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -142,7 +142,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -32,7 +32,7 @@ uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR uses MAINBOARD -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -73,7 +73,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -95,7 +95,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -135,10 +135,10 @@ #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -157,7 +157,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -201,7 +201,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## default ROM_SIZE = 256 * 1024 default ROM_SECTION_SIZE = ROM_SIZE @@ -8,18 +8,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -66,7 +66,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -74,7 +74,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds
Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -15,7 +15,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -62,7 +62,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -80,10 +80,10 @@ default HAVE_OPTION_TABLE=0
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -70,7 +70,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -78,7 +78,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -98,7 +98,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -68,7 +68,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -90,10 +90,10 @@ default HAVE_OPTION_TABLE=1
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
@@ -149,7 +149,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -5,7 +5,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -17,18 +17,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -75,7 +75,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -83,7 +83,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -103,7 +103,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -34,7 +34,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses _RAMBASE @@ -88,7 +88,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -110,7 +110,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -139,10 +139,10 @@ #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -158,12 +158,12 @@
### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### default FALLBACK_SIZE=131072
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -213,7 +213,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -2,7 +2,7 @@ ## BEGIN BOILERPLATE - DO NOT EDIT ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus payload) will live in the boot rom chip. +## (coreboot plus payload) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE # The fallback image uses FALLBACK_SIZE bytes at the end of the ROM @@ -11,7 +11,7 @@ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else -# The normal image goes at the beginning of the LinuxBIOS ROM region +# The normal image goes at the beginning of the coreboot ROM region # and uses all the remaining space
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) @@ -19,12 +19,12 @@ end
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -81,7 +81,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -89,7 +89,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if HAVE_FALLBACK_BOOT if USE_FALLBACK_IMAGE @@ -114,7 +114,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -55,7 +55,7 @@ uses ROM_SIZE uses ROM_IMAGE_SIZE uses FALLBACK_SIZE -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION
## These are defined in mainboard Config.lb, don't add here uses ROM_SECTION_SIZE @@ -143,7 +143,7 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480
### -### LinuxBIOS layout values +### coreboot layout values ###
## @@ -162,7 +162,7 @@ default USE_OPTION_TABLE = 0
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -211,7 +211,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/bus.h =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/bus.h 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/bus.h 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,7 +1,7 @@ #ifndef XE7501DEVKIT_BUS_H_INCLUDED #define XE7501DEVKIT_BUS_H_INCLUDED
-// These were determined by seeing how LinuxBIOS enumerates the various +// These were determined by seeing how coreboot enumerates the various // PCI (and PCI-like) buses on the board.
#define PCI_BUS_CHIPSET 0
Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/ioapic.h =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/ioapic.h 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/ioapic.h 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,4 +1,4 @@ -// IOAPIC addresses determined by LinuxBIOS enumeration. +// IOAPIC addresses determined by coreboot enumeration. // Someday add functions to get APIC IDs and versions from the chips themselves. #define IOAPIC_ICH3 2
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE @@ -17,18 +17,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -162,7 +162,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ##
if HAVE_FAILOVER_BOOT @@ -189,7 +189,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -223,7 +223,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -40,7 +40,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -122,7 +122,7 @@ default HAVE_FAILOVER_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -149,7 +149,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -236,10 +236,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -258,7 +258,7 @@ default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00100000
@@ -308,7 +308,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -95,7 +95,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -115,7 +115,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -145,7 +145,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -34,7 +34,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -72,7 +72,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -94,7 +94,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -131,10 +131,10 @@
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -153,7 +153,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -202,7 +202,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -92,7 +92,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -112,7 +112,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -142,7 +142,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -34,7 +34,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -72,7 +72,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -94,7 +94,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -130,10 +130,10 @@ #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -152,7 +152,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -201,7 +201,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -70,7 +70,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -78,7 +78,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -98,7 +98,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -60,7 +60,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -82,10 +82,10 @@ default HAVE_OPTION_TABLE=0
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
@@ -141,7 +141,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -26,5 +26,5 @@ dir nvram dir flash
-addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a" +addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a" makedefine CFLAGS += -g
Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -42,7 +42,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses CROSS_COMPILE uses CC uses HOSTCC @@ -89,7 +89,7 @@ default CONFIG_FS_FAT=1 default AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
-# LinuxBIOS must fit into 128KB +# coreboot must fit into 128KB default ROM_IMAGE_SIZE=131072 default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE} default PAYLOAD_SIZE=262144 @@ -108,11 +108,11 @@ ## Exception vectors (other than reset vector) default _EXCEPTION_VECTORS=_RESET+0x100
-## Start of linuxBIOS in the boot rom +## Start of coreboot in the boot rom ## = _RESET + exeception vector table size default _ROMSTART=_RESET+0x3100
-## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM default _RAMBASE=0x00100000 default _RAMSTART=0x00100000
Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpoint/sp7410.cfg =================================================================== --- trunk/coreboot-v2/src/mainboard/motorola/sandpoint/sp7410.cfg 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/motorola/sandpoint/sp7410.cfg 2008-01-18 15:08:58 UTC (rev 3053) @@ -99,7 +99,7 @@ [HOST] IP 10.0.1.11 ;FILE E:\cygnus\root\usr\demo\sp7400\vxworks -FILE linuxbios.elf +FILE coreboot.elf FORMAT ELF ;START 0x403104 LOAD MANUAL ;load code MANUAL or AUTO after reset @@ -114,7 +114,7 @@ CHIPSIZE 0x100000 ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000) BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64) WORKSPACE 0x00000000 ;workspace in SDRAM -FILE linuxbios.elf +FILE coreboot.elf FORMAT ELF ERASE 0xFFF00000 ;erase sector 0 of flash ERASE 0xFFF04000 ;erase sector 1 of flash
Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -39,7 +39,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses CROSS_COMPILE uses CC uses HOSTCC @@ -86,7 +86,7 @@ default CONFIG_FS_FAT=1 default AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
-# LinuxBIOS must fit into 128KB +# coreboot must fit into 128KB default ROM_IMAGE_SIZE=131072 default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE} default PAYLOAD_SIZE=262144 @@ -105,11 +105,11 @@ ## Exception vectors (other than reset vector) default _EXCEPTION_VECTORS=_RESET+0x100
-## Start of linuxBIOS in the boot rom +## Start of coreboot in the boot rom ## = _RESET + exeception vector table size default _ROMSTART=_RESET+0x3100
-## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM default _RAMBASE=0x00100000 default _RAMSTART=0x00100000
Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -59,7 +59,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -121,7 +121,7 @@ default LIFT_BSP_APIC_ID = 1 default CONFIG_CHIP_NAME = 1
-# Move the default LinuxBIOS CMOS range off of AMD RTC registers. +# Move the default coreboot CMOS range off of AMD RTC registers. default LB_CKS_RANGE_START = 49 default LB_CKS_RANGE_END = 122 default LB_CKS_LOC = 123
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -24,7 +24,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -36,18 +36,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -98,7 +98,7 @@ end end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ##
if USE_FALLBACK_IMAGE @@ -118,7 +118,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -142,7 +142,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -61,7 +61,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -131,7 +131,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -158,7 +158,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -238,10 +238,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -260,7 +260,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00100000
@@ -309,7 +309,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -24,7 +24,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -36,19 +36,19 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -122,7 +122,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -142,7 +142,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -180,7 +180,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -57,7 +57,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CONFIG_GDB_STUB uses CROSS_COMPILE @@ -125,7 +125,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -147,7 +147,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -218,10 +218,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -240,7 +240,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -289,7 +289,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -93,7 +93,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -113,7 +113,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -142,7 +142,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -35,7 +35,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -82,7 +82,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -104,7 +104,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -152,10 +152,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -174,7 +174,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -223,7 +223,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -21,7 +21,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE @@ -38,18 +38,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -142,7 +142,7 @@
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -170,7 +170,7 @@
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -219,7 +219,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -62,7 +62,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -146,7 +146,7 @@ default HAVE_FAILOVER_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -171,7 +171,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -257,10 +257,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -279,7 +279,7 @@ default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00100000
@@ -331,7 +331,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/olpc/btest/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/btest/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/olpc/btest/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -70,7 +70,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -78,7 +78,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -98,7 +98,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -61,7 +61,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -83,10 +83,10 @@ default HAVE_OPTION_TABLE=0
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
@@ -142,7 +142,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/olpc/rev_a/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/rev_a/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -70,7 +70,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -78,7 +78,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -98,7 +98,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -61,7 +61,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -83,10 +83,10 @@ default HAVE_OPTION_TABLE=0
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
@@ -142,7 +142,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -20,7 +20,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -32,18 +32,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -81,7 +81,7 @@
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -89,7 +89,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -109,7 +109,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -90,7 +90,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -111,10 +111,10 @@ default HAVE_OPTION_TABLE=0
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
@@ -177,7 +177,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -189,7 +189,7 @@ * etc. The stack might be used to return etc. That means we * care about what is in the stack. If we are smart we set * the CAR stack to the same location as the rest of - * LinuxBIOS. If that is the case we can just do a wbinvd. + * coreboot. If that is the case we can just do a wbinvd. * The stack will be written into real RAM that is now setup * and we continue like nothing happened. If the stack is * located somewhere other than where LB would like it, you
Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,19 +12,19 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -111,7 +111,7 @@
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -151,7 +151,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CONFIG_GDB_STUB uses CROSS_COMPILE @@ -95,7 +95,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -117,7 +117,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -185,10 +185,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x40
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -207,7 +207,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -256,7 +256,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -21,7 +21,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE @@ -38,18 +38,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -111,7 +111,7 @@
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -139,7 +139,7 @@
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -188,7 +188,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -62,7 +62,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -145,7 +145,7 @@ default HAVE_FAILOVER_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -170,7 +170,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -254,10 +254,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -276,7 +276,7 @@ default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00100000
@@ -328,7 +328,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -5,7 +5,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -17,18 +17,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can be cached to speed up linuxBIOS, +## Compute a range of ROM that can be cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -75,7 +75,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -83,7 +83,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -103,7 +103,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -34,7 +34,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses _RAMBASE @@ -75,7 +75,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -97,7 +97,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -125,10 +125,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -144,12 +144,12 @@
### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### default FALLBACK_SIZE=131072
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -199,7 +199,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -5,7 +5,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -17,18 +17,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of LinuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can be cached to speed up linuxBIOS. +## Compute a range of ROM that can be cached to speed up coreboot. ## execution speed. ## XIP_ROM_SIZE must be a power of 2. ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE @@ -74,7 +74,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -82,7 +82,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -102,7 +102,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -34,7 +34,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses _RAMBASE @@ -75,7 +75,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -97,7 +97,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -125,10 +125,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -144,12 +144,12 @@
### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### default FALLBACK_SIZE=131072
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -199,7 +199,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -5,7 +5,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -17,18 +17,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of LinuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can be cached to speed up linuxBIOS. +## Compute a range of ROM that can be cached to speed up coreboot. ## execution speed. ## XIP_ROM_SIZE must be a power of 2. ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE @@ -74,7 +74,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -82,7 +82,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -102,7 +102,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -34,7 +34,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses _RAMBASE @@ -75,7 +75,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -97,7 +97,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -125,10 +125,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -144,12 +144,12 @@
### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### default FALLBACK_SIZE=131072
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -199,7 +199,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -5,7 +5,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -17,18 +17,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -75,7 +75,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -83,7 +83,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -103,7 +103,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -34,7 +34,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses _RAMBASE @@ -75,7 +75,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -97,7 +97,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -125,10 +125,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -144,12 +144,12 @@
### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### default FALLBACK_SIZE=131072
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -199,7 +199,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -5,7 +5,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -17,18 +17,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -75,7 +75,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -83,7 +83,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -103,7 +103,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -34,7 +34,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses _RAMBASE @@ -75,7 +75,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -97,7 +97,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -125,10 +125,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -144,12 +144,12 @@
### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### default FALLBACK_SIZE=131072
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -199,7 +199,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/technologic/ts5300/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/technologic/ts5300/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## default ROM_SIZE = 128 * 1024 default FALLBACK_SIZE = 0x10000 @@ -14,18 +14,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -71,7 +71,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -79,7 +79,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -99,7 +99,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -12,7 +12,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -86,7 +86,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -103,10 +103,10 @@ default HAVE_OPTION_TABLE=1
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
Modified: trunk/coreboot-v2/src/mainboard/totalimpact/briq/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/totalimpact/briq/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/totalimpact/briq/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -46,4 +46,4 @@ ## Build the objects we have code for in this directory. ##
-addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a" +addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a"
Modified: trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -39,7 +39,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses CROSS_COMPILE uses CC uses HOSTCC @@ -108,11 +108,11 @@ ## Exception vectors (other than reset vector) default _EXCEPTION_VECTORS=_RESET+0x100
-## Start of linuxBIOS in the boot rom +## Start of coreboot in the boot rom ## = _RESET + exeception vector table size default _ROMSTART=_RESET+0x3100
-## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM default _RAMBASE=0x00100000 default _RAMSTART=0x00100000
Modified: trunk/coreboot-v2/src/mainboard/totalimpact/briq/briQ7400.cfg =================================================================== --- trunk/coreboot-v2/src/mainboard/totalimpact/briq/briQ7400.cfg 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/totalimpact/briq/briQ7400.cfg 2008-01-18 15:08:58 UTC (rev 3053) @@ -148,7 +148,7 @@ CHIPSIZE 0x100000 ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000) BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64) ;WORKSPACE 0x00000000 ;workspace in SDRAM -FILE linuxbios.rom +FILE coreboot.rom FORMAT ELF ERASE 0xFFF00000 ;erase sector 0 of flash ERASE 0xFFF10000 ;erase sector 1 of flash
Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,19 +12,19 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -107,7 +107,7 @@
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -137,7 +137,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -36,7 +36,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CONFIG_GDB_STUB uses CROSS_COMPILE @@ -87,7 +87,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -114,7 +114,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -162,10 +162,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2735
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -184,7 +184,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -233,7 +233,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/cache_as_ram_auto.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/cache_as_ram_auto.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -259,7 +259,7 @@ print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n"); #endif - /*copy and execute linuxbios_ram */ + /*copy and execute coreboot_ram */ copy_and_run(new_cpu_reset); /* We will not return */ }
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@
end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -110,7 +110,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -140,7 +140,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -35,7 +35,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -83,7 +83,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -105,7 +105,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -153,10 +153,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -175,7 +175,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -224,7 +224,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@
end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -110,7 +110,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -140,7 +140,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -35,7 +35,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -84,7 +84,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -106,7 +106,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -154,10 +154,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -176,7 +176,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -225,7 +225,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@
end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -110,7 +110,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -140,7 +140,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -35,7 +35,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -83,7 +83,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -105,7 +105,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -153,10 +153,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -175,7 +175,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -224,7 +224,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@
end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -110,7 +110,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -140,7 +140,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -35,7 +35,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -88,7 +88,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -110,7 +110,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -170,10 +170,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -192,7 +192,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -241,7 +241,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@
end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -110,7 +110,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -140,7 +140,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -35,7 +35,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -83,7 +83,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -105,7 +105,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -153,10 +153,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -175,7 +175,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -224,7 +224,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -90,7 +90,7 @@
end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -110,7 +110,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -140,7 +140,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -35,7 +35,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -94,7 +94,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -116,7 +116,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -180,10 +180,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -202,7 +202,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -251,7 +251,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,19 +12,19 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -98,7 +98,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -119,7 +119,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -157,7 +157,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -35,7 +35,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CONFIG_GDB_STUB uses CROSS_COMPILE @@ -101,7 +101,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -123,7 +123,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -189,10 +189,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -211,7 +211,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -260,7 +260,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,19 +12,19 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -98,7 +98,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -118,7 +118,7 @@ end
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -156,7 +156,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -35,7 +35,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CONFIG_GDB_STUB uses CROSS_COMPILE @@ -94,7 +94,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -116,7 +116,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -176,10 +176,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -198,7 +198,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -247,7 +247,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE @@ -17,18 +17,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -102,7 +102,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -130,7 +130,7 @@
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -185,7 +185,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -38,7 +38,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CONFIG_GDB_STUB uses CROSS_COMPILE @@ -106,7 +106,7 @@ default HAVE_FAILOVER_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -128,7 +128,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -197,10 +197,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -219,7 +219,7 @@ default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00100000
@@ -268,7 +268,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -21,7 +21,7 @@
## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE @@ -38,18 +38,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -112,7 +112,7 @@
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -140,7 +140,7 @@
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -189,7 +189,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -62,7 +62,7 @@ uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -146,7 +146,7 @@ default HAVE_FAILOVER_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -173,7 +173,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -259,10 +259,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -281,7 +281,7 @@ default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00100000
@@ -333,7 +333,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,19 +12,19 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -100,7 +100,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -121,7 +121,7 @@
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -152,7 +152,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -87,7 +87,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -109,7 +109,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -162,10 +162,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -184,7 +184,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000
@@ -233,7 +233,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,19 +12,19 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -100,7 +100,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -121,7 +121,7 @@
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -152,7 +152,7 @@ end
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -35,7 +35,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD uses TTYS0_BASE @@ -87,7 +87,7 @@ default HAVE_FALLBACK_BOOT=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1
@@ -109,7 +109,7 @@ default HAVE_OPTION_TABLE=1
## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -161,10 +161,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536
## @@ -183,7 +183,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00002000
@@ -232,7 +232,7 @@ default TTYS0_LCS=0x3
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately
Modified: trunk/coreboot-v2/src/mainboard/via/epia/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/via/epia/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -69,7 +69,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -77,7 +77,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -97,7 +97,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/via/epia/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/via/epia/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -20,7 +20,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -82,7 +82,7 @@ default HAVE_MP_TABLE=0
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -107,10 +107,10 @@ default HAVE_OPTION_TABLE=1
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@
## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -76,7 +76,7 @@ end
## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -84,7 +84,7 @@ ldscript /cpu/x86/32bit/entry32.lds
## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -104,7 +104,7 @@ ldscript /arch/i386/lib/id.lds
### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ###
Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,7 +10,7 @@ uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -71,7 +71,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0
@@ -94,10 +94,10 @@ default HAVE_OPTION_TABLE=1
### -### LinuxBIOS layout values +### coreboot layout values ###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072
Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/acpi_tables.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/acpi_tables.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,5 +1,5 @@ /* - * LinuxBIOS ACPI Table support + * coreboot ACPI Table support * written by Stefan Reinauer stepan@openbios.org * ACPI FADT, FACS, and DSDT table support added by * Nick Barker nick.barker9@btinternet.com, and those portions
Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/mainboard.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/mainboard.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -13,7 +13,7 @@ // we do this right here because: // - all the hardware is working, and some VGA bioses seem to need // that - // - we need page 0 below for linuxbios tables. + // - we need page 0 below for coreboot tables.
printk_debug("INSTALL REAL-MODE IDT\n"); setup_realmode_idt();
Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/vgabios.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/vgabios.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/vgabios.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -66,7 +66,7 @@ *--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used - without reliance on other parts of core Linuxbios + without reliance on other parts of core coreboot (C) 2005 Nick.Barker9@btinternet.com
Used initially for epia-m where there are problems getting the bios @@ -399,10 +399,10 @@ // that simplifies a lot of things ... // we'll just push all the registers on the stack as longwords, // and pop to protected mode. -// second, since this only ever runs as part of linuxbios, +// second, since this only ever runs as part of coreboot, // we know all the segment register values -- so we don't save any. // keep the handler that calls things small. It can do a call to -// more complex code in linuxbios itself. This helps a lot as we don't +// more complex code in coreboot itself. This helps a lot as we don't // have to do address fixup in this little stub, and calls are absolute // so the handler is relocatable. void handler(void)
Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10.h =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10.h 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10.h 2008-01-18 15:08:58 UTC (rev 3053) @@ -1019,7 +1019,7 @@ u32 up_planes; // down planes will be [up_planes, planes) } __attribute__((packed));
-/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by linuxbios_car and linuxbios_ram stage. and linuxbios_ram may be running at 64bit later.*/ +/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/ #if CONFIG_AMDMCT == 0
//#define MEM_CS_COPY 1
Modified: trunk/coreboot-v2/src/northbridge/amd/amdht/comlib.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdht/comlib.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/northbridge/amd/amdht/comlib.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -206,14 +206,14 @@
void CALLCONV AmdPCIRead(SBDFO loc, u32 *Value) { - /* Use LinuxBIOS PCI functions */ + /* Use coreboot PCI functions */ *Value = pci_read_config32((loc & 0xFFFFF000), SBDFO_OFF(loc)); }
void CALLCONV AmdPCIWrite(SBDFO loc, u32 *Value) { - /* Use LinuxBIOS PCI functions */ + /* Use coreboot PCI functions */ pci_write_config32((loc & 0xFFFFF000), SBDFO_OFF(loc), *Value); }
Modified: trunk/coreboot-v2/src/northbridge/amd/amdht/comlib.h =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdht/comlib.h 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/northbridge/amd/amdht/comlib.h 2008-01-18 15:08:58 UTC (rev 3053) @@ -26,7 +26,7 @@
#include "porting.h"
-/* include LinuxBIOS pci functions */ +/* include coreboot pci functions */ #include <device/pci_def.h> #include <device/pci_ids.h>
Modified: trunk/coreboot-v2/src/northbridge/amd/amdht/ht_wrapper.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdht/ht_wrapper.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/northbridge/amd/amdht/ht_wrapper.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -124,7 +124,7 @@ /** * void amd_ht_init(struct sys_info *sysinfo) * - * AMD HT init LinuxBIOS wrapper + * AMD HT init coreboot wrapper * */ void amd_ht_init(struct sys_info *sysinfo)
Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f_dqs.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -2003,7 +2003,7 @@ train_ram(nodeid, sysinfo, sysinfox); #else /* Can copy dqs_timing to ap cache and run from cache? - * we need linuxbios_ap_car.rom? and treat it as linuxbios_ram.rom for ap ? + * we need coreboot_ap_car.rom? and treat it as coreboot_ram.rom for ap ? */ copy_and_run_ap_code_in_car(retcall); // will go back by jump
Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctmtr_d.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctmtr_d.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctmtr_d.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -75,7 +75,7 @@ Set default values for CPU registers ======================================================================*/
- /* NOTE : For LinuxBIOS, we don't need to set mtrr enables here because + /* NOTE : For coreboot, we don't need to set mtrr enables here because they are still enable from cache_as_ram.inc */
addr = 0x250; @@ -88,7 +88,7 @@ /*====================================================================== Set variable MTRR values ======================================================================*/ - /* NOTE: for LinuxBIOS change from 0x200 to 0x204: LinuxBIOS is using + /* NOTE: for coreboot change from 0x200 to 0x204: coreboot is using 0x200, 0x201 for [1M, CONFIG_TOP_MEM) 0x202, 0x203 for ROM Caching */
Modified: trunk/coreboot-v2/src/northbridge/amd/gx2/chipsetinit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx2/chipsetinit.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/northbridge/amd/gx2/chipsetinit.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -295,7 +295,7 @@ outb( P80_CHIPSET_INIT, 0x80); ChipsetGeodeLinkInit(); #if 0 - /* we hope NEVER to be in linuxbios when S3 resumes + /* we hope NEVER to be in coreboot when S3 resumes if (! IsS3Resume()) */ { struct acpiinit *aci = acpi_init_table;
Modified: trunk/coreboot-v2/src/northbridge/intel/i855pm/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i855pm/raminit.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/northbridge/intel/i855pm/raminit.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -1358,7 +1358,7 @@ }
- /* I have finally seen ram bad enough to cause LinuxBIOS + /* I have finally seen ram bad enough to cause coreboot * to die in mysterious ways, before booting up far * enough to run a memory tester. This code attempts * to catch this blatantly bad ram, with a spot check.
Modified: trunk/coreboot-v2/src/northbridge/motorola/mpc107/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/motorola/mpc107/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/northbridge/motorola/mpc107/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,5 +1,5 @@ # -# Objects linked with linuxbios +# Objects linked with coreboot #
config chip.h
Modified: trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -36,7 +36,7 @@ /* * pci_domain_set_resources creates memory resources describing the * fixed memory on the system. This is not actually used anywhere - * except when the linuxbios table is generated. + * except when the coreboot table is generated. */ static void pci_domain_set_resources(device_t dev) {
Modified: trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -121,7 +121,7 @@ /* these are ENDING addresses, not sizes. * if there is memory in this slot, then reg will be > rambits. * So we just take the max, that gives us total. - * We take the highest one to cover for once and future linuxbios + * We take the highest one to cover for once and future coreboot * bugs. We warn about bugs. */ if (reg > rambits)
Modified: trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -158,7 +158,7 @@
#else
- /* code to make vga init run in real mode - does work but against the current Linuxbios philosophy */ + /* code to make vga init run in real mode - does work but against the current coreboot philosophy */ printk_debug("INSTALL REAL-MODE IDT\n"); setup_realmode_idt(); printk_debug("DO THE VGA BIOS\n"); @@ -293,7 +293,7 @@ /* these are ENDING addresses, not sizes. * if there is memory in this slot, then reg will be > rambits. * So we just take the max, that gives us total. - * We take the highest one to cover for once and future linuxbios + * We take the highest one to cover for once and future coreboot * bugs. We warn about bugs. */ if (reg > rambits)
Modified: trunk/coreboot-v2/src/northbridge/via/vt8623/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8623/raminit.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/northbridge/via/vt8623/raminit.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -28,7 +28,7 @@ 256 Mb 266Mhz 2 Bank (i.e. double sided) 512 Mb 266Mhz 2 Bank (i.e. double sided) */ -/* ported and enhanced from assembler level code in Linuxbios v1 */ +/* ported and enhanced from assembler level code in coreboot v1 */
#include <cpu/x86/mtrr.h> #include "raminit.h"
Modified: trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_vga.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_vga.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_vga.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -448,7 +448,7 @@ #endif
/** - * LinuxBIOS management part + * coreboot management part * @param[in] dev Info about the PCI device to initialise */ static void cs5530_vga_init(device_t dev)
Modified: trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -511,7 +511,7 @@
post_code(P80_CHIPSET_INIT);
- /* we hope NEVER to be in linuxbios when S3 resumes + /* we hope NEVER to be in coreboot when S3 resumes if (! IsS3Resume()) */ { struct acpiinit *aci = acpi_init_table;
Modified: trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -185,7 +185,7 @@ byte |= (1<<0); // SATA enable pci_write_config8(dev, 0x84, byte);
-// wdt and cf9 for later in linuxbios_ram to call hard_reset +// wdt and cf9 for later in coreboot_ram to call hard_reset bcm5785_enable_wdt_port_cf9();
bcm5785_enable_msg();
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -28,7 +28,7 @@ outb(0x80, 0x80); }
-// See http://openbios.org/pipermail/linuxbios/2004-September/009077.html +// See http://www.coreboot.org/pipermail/linuxbios/2004-September/009077.html // for a description of this function. static int smbus_wait_until_active(void) {
Modified: trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c =================================================================== --- trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -18,7 +18,7 @@ * MA 02110-1301 USA */ /* (C) Copyright 2005 Nick Barker <nick.barker@btinternet.com - brought into line with the current architecture of LinuxBios */ + brought into line with the current architecture of coreboot */
#include <arch/io.h>
Modified: trunk/coreboot-v2/src/stream/rom_stream.c =================================================================== --- trunk/coreboot-v2/src/stream/rom_stream.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/stream/rom_stream.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -84,7 +84,7 @@ dest = (CONFIG_LB_MEM_TOPK<<10); } #endif - if((dest < (unsigned char *) 0xf0000) && ((dest+olen)> (unsigned char *)0xf0000)) { //linuxbios tables etc + if((dest < (unsigned char *) 0xf0000) && ((dest+olen)> (unsigned char *)0xf0000)) { // coreboot tables etc dest = (unsigned char *) (CONFIG_LB_MEM_TOPK<<10); } #endif
Modified: trunk/coreboot-v2/src/superio/smsc/lpc47n217/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/smsc/lpc47n217/superio.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/src/superio/smsc/lpc47n217/superio.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -22,7 +22,7 @@ */
/* RAM-based driver for SMSC LPC47N217 Super I/O chip. */ -/* Based on LinuxBIOS code for SMSC 47B397. */ +/* Based on coreboot code for SMSC 47B397. */
#include <arch/io.h> #include <device/device.h>
Modified: trunk/coreboot-v2/targets/a-trend/atc-6220/Config.lb =================================================================== --- trunk/coreboot-v2/targets/a-trend/atc-6220/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/a-trend/atc-6220/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -36,14 +36,14 @@
romimage "normal" option USE_FALLBACK_IMAGE = 0 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/advantech/pcm-5820/Config.lb =================================================================== --- trunk/coreboot-v2/targets/advantech/pcm-5820/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/advantech/pcm-5820/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -41,14 +41,14 @@
romimage "normal" option USE_FALLBACK_IMAGE = 0 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/agami/aruma/Config.lb =================================================================== --- trunk/coreboot-v2/targets/agami/aruma/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/agami/aruma/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -14,7 +14,7 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x17000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0-normal" + option COREBOOT_EXTRA_VERSION=".0-normal" payload ../../../../../../filo.elf end
@@ -22,7 +22,7 @@ option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x17000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0-fallback" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload ../../../../../../filo.elf end
Modified: trunk/coreboot-v2/targets/agami/aruma/Config1M.lb =================================================================== --- trunk/coreboot-v2/targets/agami/aruma/Config1M.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/agami/aruma/Config1M.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -17,7 +17,7 @@ option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x14000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0-big" + option COREBOOT_EXTRA_VERSION=".0-big" payload ../../../../../../linux.elf end
Modified: trunk/coreboot-v2/targets/amd/db800/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/db800/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/amd/db800/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -42,7 +42,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=64*1024 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" payload ../payload.elf end
Modified: trunk/coreboot-v2/targets/amd/norwich/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/norwich/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/amd/norwich/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -42,7 +42,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=64*1024 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" payload ../payload.elf end
Modified: trunk/coreboot-v2/targets/amd/rumba/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/rumba/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/amd/rumba/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -9,7 +9,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi @@ -21,7 +21,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebia @@ -30,4 +30,4 @@ payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/amd/rumba/Config.nofallback.lb =================================================================== --- trunk/coreboot-v2/targets/amd/rumba/Config.nofallback.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/amd/rumba/Config.nofallback.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -11,7 +11,7 @@ #romimage "normal" # option USE_FALLBACK_IMAGE=0 # option ROM_IMAGE_SIZE=0x10000 -# option LINUXBIOS_EXTRA_VERSION=".0Normal" +# option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi @@ -23,7 +23,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebia @@ -33,6 +33,6 @@ # payload /home/ollie/work/filo-0.4.1/filo.elf end
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" -buildrom ./linuxbios.rom ROM_SIZE "fallback" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback"
Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -14,14 +14,14 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0-normal" + option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end
romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0-fallback" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -20,7 +20,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -48,7 +48,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -77,9 +77,9 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" -#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -14,7 +14,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0-fallback" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end
@@ -23,7 +23,7 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION=".0-failover" + option COREBOOT_EXTRA_VERSION=".0-failover" end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" "failover" \ No newline at end of file +buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" \ No newline at end of file
Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -41,7 +41,7 @@ # option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x30000 # option XIP_ROM_SIZE=0x40000 -# option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" +# option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../payload.elf #end
@@ -53,7 +53,7 @@ option ROM_IMAGE_SIZE=0x3f000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../payload.elf end
@@ -62,7 +62,7 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end
#buildrom ./amd-cheetah-fam10.rom ROM_SIZE "normal" "fallback" "failover"
Modified: trunk/coreboot-v2/targets/arima/hdama/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/arima/hdama/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/arima/hdama/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -14,14 +14,14 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0-normal" + option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end
romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0-fallback" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb =================================================================== --- trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -48,7 +48,7 @@ uses CONFIG_CHIP_CONFIGURE uses XIP_ROM_SIZE uses XIP_ROM_BASE -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION
option CONFIG_CHIP_CONFIGURE=1
@@ -73,17 +73,17 @@
### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### option FALLBACK_SIZE=ROM_SIZE
-## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM option _RAMBASE=0x00004000
# ### ### Compute the start location and size size of -### The linuxBIOS bootloader. +### The coreboot bootloader. ###
# @@ -92,7 +92,7 @@ option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 # option ROM_SECTION_SIZE=0x100000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" mainboard arima/hdama # payload ../../../../tg3--ide_disk.zelf payload ../../../../opteron_phase1_p4_noapic
Modified: trunk/coreboot-v2/targets/arima/hdama/Config.lb =================================================================== --- trunk/coreboot-v2/targets/arima/hdama/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/arima/hdama/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -12,7 +12,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" payload ../../../payloads/filo.elf # payload /etc/hosts end @@ -20,9 +20,9 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" payload ../../../payloads/filo.elf # payload /etc/hosts end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb =================================================================== --- trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -9,7 +9,7 @@ option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
-## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use +## ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). ## leave 36k for vsa and 32K for video ROM #option ROM_SIZE = 1024*256 - 36*1024 - 32 * 1024 @@ -17,7 +17,7 @@ #No VGA for now option ROM_SIZE = 1024*512 - 36*1024
-# ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image, +# ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, ## not including any payload. option ROM_IMAGE_SIZE=64*1024
@@ -27,7 +27,7 @@ option MAXIMUM_CONSOLE_LOGLEVEL = 11 romimage "fallback" option USE_FALLBACK_IMAGE=1 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" payload ../payload.elf end
Modified: trunk/coreboot-v2/targets/asi/mb_5blmp/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asi/mb_5blmp/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/asi/mb_5blmp/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -28,16 +28,16 @@ romimage "normal" option USE_FALLBACK_IMAGE = 0 option ROM_IMAGE_SIZE = 64 * 1024 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 option ROM_IMAGE_SIZE = 64 * 1024 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" -# buildrom ./linuxbios.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +# buildrom ./coreboot.rom ROM_SIZE "fallback"
Modified: trunk/coreboot-v2/targets/asus/a8n_e/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asus/a8n_e/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/asus/a8n_e/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -27,7 +27,7 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="_Normal" + option COREBOOT_EXTRA_VERSION="_Normal" payload /tmp/filo.elf end
@@ -36,7 +36,7 @@ option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="_Fallback" + option COREBOOT_EXTRA_VERSION="_Fallback" payload /tmp/filo.elf end
@@ -45,8 +45,8 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION="_Failover" + option COREBOOT_EXTRA_VERSION="_Failover" end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" -#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/asus/a8v-e_se/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asus/a8v-e_se/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/asus/a8v-e_se/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -24,15 +24,15 @@ option ROM_SIZE = 512 * 1024 option USE_FALLBACK_IMAGE = 0 option ROM_IMAGE_SIZE = 128 * 1024 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" payload /tmp/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 option ROM_IMAGE_SIZE = 128 * 1024 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/asus/mew-am/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asus/mew-am/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/asus/mew-am/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -36,14 +36,14 @@
romimage "normal" option USE_FALLBACK_IMAGE = 0 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/asus/mew-vm/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asus/mew-vm/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/asus/mew-vm/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -9,7 +9,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" # payload /etc/hosts payload /home/amp/filo-0.5/filo.elf end @@ -17,9 +17,9 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /etc/hosts payload /home/amp/filo-0.5/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/asus/p2b/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asus/p2b/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/asus/p2b/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -36,14 +36,14 @@
romimage "normal" option USE_FALLBACK_IMAGE = 0 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/asus/p2b-f/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asus/p2b-f/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/asus/p2b-f/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -36,14 +36,14 @@
romimage "normal" option USE_FALLBACK_IMAGE = 0 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/asus/p3b-f/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asus/p3b-f/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/asus/p3b-f/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -36,14 +36,14 @@
romimage "normal" option USE_FALLBACK_IMAGE = 0 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/axus/tc320/Config.lb =================================================================== --- trunk/coreboot-v2/targets/axus/tc320/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/axus/tc320/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -18,7 +18,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## See also: http://linuxbios.org/AXUS_WINTERM_Build_Tutorial +## See also: http://coreboot.org/AXUS_WINTERM_Build_Tutorial
target tc320 mainboard axus/tc320 @@ -38,14 +38,14 @@
romimage "normal" option USE_FALLBACK_IMAGE = 0 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload ../../../../../../../images/etherboot.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload ../../../../../../../images/etherboot.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/azza/pt-6ibd/Config.lb =================================================================== --- trunk/coreboot-v2/targets/azza/pt-6ibd/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/azza/pt-6ibd/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -36,14 +36,14 @@
romimage "normal" option USE_FALLBACK_IMAGE = 0 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/bcom/winnet100/Config.lb =================================================================== --- trunk/coreboot-v2/targets/bcom/winnet100/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/bcom/winnet100/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -18,7 +18,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## See also: http://www.linuxbios.org/BCOM_WINNET100_Build_Tutorial +## See also: http://www.coreboot.org/BCOM_WINNET100_Build_Tutorial
target winnet100 mainboard bcom/winnet100 @@ -39,15 +39,15 @@ romimage "normal" option USE_FALLBACK_IMAGE = 0 option ROM_IMAGE_SIZE = 64 * 1024 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload ../../../../../../../images/etherboot.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 option ROM_IMAGE_SIZE = 64 * 1024 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload ../../../../../../../images/etherboot.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/biostar/m6tba/Config.lb =================================================================== --- trunk/coreboot-v2/targets/biostar/m6tba/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/biostar/m6tba/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -37,14 +37,14 @@
romimage "normal" option USE_FALLBACK_IMAGE = 0 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/broadcom/blast/Config.lb =================================================================== --- trunk/coreboot-v2/targets/broadcom/blast/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/broadcom/blast/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -18,7 +18,7 @@ # option ROM_IMAGE_SIZE=0x15000 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -43,7 +43,7 @@ # option ROM_IMAGE_SIZE=0x15000 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -62,4 +62,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/buildtarget =================================================================== --- trunk/coreboot-v2/targets/buildtarget 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/buildtarget 2008-01-18 15:08:58 UTC (rev 3053) @@ -3,7 +3,7 @@ # Target build script
if [ $# -lt 1 ]; then - echo "usage: buildtarget target [path-to-linuxbios]" + echo "usage: buildtarget target [path-to-coreboot]" exit 1 fi
@@ -44,7 +44,7 @@ mkdir -p $build_dir fi if [ ! -f $config_py ]; then - echo "No linuxbios config script found. Rebuilding it.." + echo "No coreboot config script found. Rebuilding it.." $PYTHON $yapps2_py $config_g $config_py fi
Modified: trunk/coreboot-v2/targets/compaq/deskpro_en_sff_p600/Config.lb =================================================================== --- trunk/coreboot-v2/targets/compaq/deskpro_en_sff_p600/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/compaq/deskpro_en_sff_p600/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -36,14 +36,14 @@
romimage "normal" option USE_FALLBACK_IMAGE = 0 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/dell/s1850/Config.lb =================================================================== --- trunk/coreboot-v2/targets/dell/s1850/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/dell/s1850/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -8,7 +8,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x16000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" # payload ../../../payloads/filo.elf payload /tmp/filo.elf end @@ -16,9 +16,9 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x16000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload ../../../payloads/filo.elf payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/digitallogic/adl855pc/Config.lb =================================================================== --- trunk/coreboot-v2/targets/digitallogic/adl855pc/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/digitallogic/adl855pc/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -9,15 +9,15 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" payload /etc/hosts end
romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" payload /etc/hosts end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -19,8 +19,8 @@ # option ROM_IMAGE_SIZE=32 * 1024 # 0x8000 option ROM_IMAGE_SIZE=128 * 1024 # 0x10000 # option ROM_IMAGE_SIZE=512 * 1024 # 0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" payload __PAYLOAD__ end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback"
Modified: trunk/coreboot-v2/targets/digitallogic/msm586seg/Config.lb =================================================================== --- trunk/coreboot-v2/targets/digitallogic/msm586seg/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/digitallogic/msm586seg/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -12,7 +12,7 @@ #romimage "normal" # option USE_FALLBACK_IMAGE=0 # option ROM_IMAGE_SIZE=0x10000 -# option LINUXBIOS_EXTRA_VERSION=".0Normal" +# option COREBOOT_EXTRA_VERSION=".0Normal" # payload /etc/hosts #end
@@ -24,9 +24,9 @@ # option ROM_IMAGE_SIZE=32 * 1024 # 0x8000 option ROM_IMAGE_SIZE=128 * 1024 # 0x10000 # option ROM_IMAGE_SIZE=512 * 1024 # 0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" payload ../../filo.elf # payload ../../eepro100--ide_disk.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback"
Modified: trunk/coreboot-v2/targets/digitallogic/msm800sev/Config.lb =================================================================== --- trunk/coreboot-v2/targets/digitallogic/msm800sev/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/digitallogic/msm800sev/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -5,13 +5,13 @@
option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use +## ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). ## leave 36k for vsa ## option ROM_SIZE = 1024*1024 - 36 * 1024
-## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image, +## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, ## not including any payload. option ROM_IMAGE_SIZE=64*1024
@@ -21,8 +21,8 @@ option MAXIMUM_CONSOLE_LOGLEVEL = 11 romimage "fallback" option USE_FALLBACK_IMAGE=1 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" payload ../payload.elf end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback"
Modified: trunk/coreboot-v2/targets/eaglelion/5bcm/Config.lb =================================================================== --- trunk/coreboot-v2/targets/eaglelion/5bcm/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/eaglelion/5bcm/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -9,7 +9,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi @@ -20,7 +20,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebia @@ -28,4 +28,4 @@ payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/embeddedplanet/ep405pc/Config.lb =================================================================== --- trunk/coreboot-v2/targets/embeddedplanet/ep405pc/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/embeddedplanet/ep405pc/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -43,7 +43,7 @@ ## Board has fixed size RAM option EMBEDDED_RAM_SIZE=64*1024*1024
- ## LinuxBIOS C code runs at this location in RAM + ## Coreboot C code runs at this location in RAM option _RAMBASE=0x00100000
## @@ -70,12 +70,12 @@ ## Exception vectors option _EXCEPTION_VECTORS=_ROMBASE+0x100
- ## linuxBIOS ROM start address + ## coreboot ROM start address option _ROMSTART=0xfff03000
- ## linuxBIOS C code runs at this location in RAM + ## coreboot C code runs at this location in RAM option _RAMBASE=0x00100000
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" +buildrom ./coreboot.rom ROM_SIZE "normal"
Modified: trunk/coreboot-v2/targets/emulation/qemu-i386/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/emulation/qemu-i386/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/emulation/qemu-i386/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -14,7 +14,7 @@
romimage "image" option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION="-OpenBIOS" + option COREBOOT_EXTRA_VERSION="-OpenBIOS" payload __PAYLOAD__ end
Modified: trunk/coreboot-v2/targets/emulation/qemu-i386/Config.OLPC.lb =================================================================== --- trunk/coreboot-v2/targets/emulation/qemu-i386/Config.OLPC.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/emulation/qemu-i386/Config.OLPC.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -14,9 +14,9 @@
romimage "image" option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION="-OpenBIOS" + option COREBOOT_EXTRA_VERSION="-OpenBIOS" payload /tmp/olpcpayload.elf end
-buildrom ./linuxbios.rom ROM_SIZE "image" +buildrom ./coreboot.rom ROM_SIZE "image"
Modified: trunk/coreboot-v2/targets/emulation/qemu-i386/Config.lb =================================================================== --- trunk/coreboot-v2/targets/emulation/qemu-i386/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/emulation/qemu-i386/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -12,7 +12,7 @@
romimage "image" option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION="-GRUB2" + option COREBOOT_EXTRA_VERSION="-GRUB2" payload /home/stepan/core.img end
Modified: trunk/coreboot-v2/targets/gigabyte/ga-6bxc/Config.lb =================================================================== --- trunk/coreboot-v2/targets/gigabyte/ga-6bxc/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/gigabyte/ga-6bxc/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -36,14 +36,14 @@
romimage "normal" option USE_FALLBACK_IMAGE = 0 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,7 +30,7 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x28000 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION=".0-Normal" + option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end
@@ -39,7 +39,7 @@ option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION=".0-Fallback" + option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end
@@ -48,8 +48,8 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION=".0-Failover" + option COREBOOT_EXTRA_VERSION=".0-Failover" end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
Modified: trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -31,7 +31,7 @@ option USE_FAILOVER_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" payload ../../../../payloads/filo_uda1.elf end
@@ -40,7 +40,7 @@ option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../../../../payloads/filo_uda1.elf end
@@ -49,8 +49,8 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end
-# buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" - buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" +# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" + buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
Modified: trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/README =================================================================== --- trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/README 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/README 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,3 +1,3 @@ ## How to append VGA bios?
-cat 6330VGA.rom ga_2761gxdk/linuxbios.rom > ga_2761gxdk.bin +cat 6330VGA.rom ga_2761gxdk/coreboot.rom > ga_2761gxdk.bin
Modified: trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -27,7 +27,7 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION=".0-Normal" + option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end
@@ -35,8 +35,8 @@ option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION=".0-Fallback" + option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/gigabyte/m57sli/Config.lb =================================================================== --- trunk/coreboot-v2/targets/gigabyte/m57sli/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/gigabyte/m57sli/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -39,7 +39,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -67,7 +67,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -97,8 +97,8 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
Modified: trunk/coreboot-v2/targets/gigabyte/m57sli/Config.lb.kernel =================================================================== --- trunk/coreboot-v2/targets/gigabyte/m57sli/Config.lb.kernel 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/gigabyte/m57sli/Config.lb.kernel 2008-01-18 15:08:58 UTC (rev 3053) @@ -37,7 +37,7 @@ # option ROM_IMAGE_SIZE=0x15800 # option ROM_IMAGE_SIZE=0x13800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -69,9 +69,9 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" "failover" -#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/ibm/e325/Config.lb =================================================================== --- trunk/coreboot-v2/targets/ibm/e325/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/ibm/e325/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -8,7 +8,7 @@ # ### ### Compute the start location and size size of -### The linuxBIOS bootloader. +### The coreboot bootloader. ###
# @@ -16,7 +16,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" # payload ../../filo.elf payload ../../../payloads/filo.elf end @@ -24,11 +24,11 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload ../../filo.elf payload ../../../payloads/filo.elf # use this to test a build if you don't have the etherboot # payload /etc/hosts end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/ibm/e326/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/ibm/e326/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/ibm/e326/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -14,14 +14,14 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0-normal" + option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end
romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0-fallback" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/ibm/e326/Config.lb =================================================================== --- trunk/coreboot-v2/targets/ibm/e326/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/ibm/e326/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -6,13 +6,13 @@
### ### Compute the start location and size size of -### The linuxBIOS bootloader. +### The coreboot bootloader. ###
romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" # payload ../../filo.elf payload ../../../payloads/filo.elf end @@ -20,11 +20,11 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload ../../filo.elf payload ../../../payloads/filo.elf # use this to test a build if you don't have the etherboot # payload /etc/hosts end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/iei/juki-511p/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/iei/juki-511p/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/iei/juki-511p/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -8,22 +8,22 @@ option ROM_SIZE=256*1024 ### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### option FALLBACK_SIZE=128*1024
romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=64*1024 - option LINUXBIOS_EXTRA_VERSION=".0-Normal" + option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end
romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=64*1024 - option LINUXBIOS_EXTRA_VERSION=".0-Fallback" + option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/iei/juki-511p/Config.lb =================================================================== --- trunk/coreboot-v2/targets/iei/juki-511p/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/iei/juki-511p/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -30,8 +30,8 @@
romimage "image" option ROM_IMAGE_SIZE=64*1024 - option LINUXBIOS_EXTRA_VERSION="-filo" + option COREBOOT_EXTRA_VERSION="-filo" payload ../../filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "image" +buildrom ./coreboot.rom ROM_SIZE "image"
Modified: trunk/coreboot-v2/targets/iei/nova4899r/Config.lb =================================================================== --- trunk/coreboot-v2/targets/iei/nova4899r/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/iei/nova4899r/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -39,9 +39,9 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=64*1024 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" - payload /opt/linuxbios-SVN/filo.elf + option COREBOOT_EXTRA_VERSION=".0Fallback" + payload /opt/coreboot-SVN/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback" #"normal"
Modified: trunk/coreboot-v2/targets/intel/xe7501devkit/Config.lb =================================================================== --- trunk/coreboot-v2/targets/intel/xe7501devkit/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/intel/xe7501devkit/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,11 +1,11 @@ target xe7501devkit mainboard intel/xe7501devkit
-## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use +## ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). option ROM_SIZE = 192*1024
-## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image, +## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, ## not including any payload. option ROM_IMAGE_SIZE = 0x1B000
@@ -17,7 +17,7 @@
romimage "normal" option USE_FALLBACK_IMAGE=0 -# option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" +# option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../../../../../memtest86/memtest # payload ../../../../../../../etherboot/src/bin/e1000.zelf payload ../../../../../../../etherboot/src/bin/e1000--filo.zelf @@ -28,10 +28,10 @@ # Thus no support for fallback boot. #romimage "fallback" # option USE_FALLBACK_IMAGE=1 -# option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" +# option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../../../../../memtest86/memtest # payload ../../../../../../../etherboot/src/bin/e1000.zelf # payload ../../../../../../../etherboot/src/bin/e1000--filo.zelf #end
-buildrom ./linuxbios.rom ROM_SIZE "normal" +buildrom ./coreboot.rom ROM_SIZE "normal"
Modified: trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -12,14 +12,14 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x17000 - option LINUXBIOS_EXTRA_VERSION=".0-normal" + option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end
romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x17000 - option LINUXBIOS_EXTRA_VERSION=".0-fallback" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/iwill/dk8_htx/Config.lb =================================================================== --- trunk/coreboot-v2/targets/iwill/dk8_htx/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/iwill/dk8_htx/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -17,7 +17,7 @@ # option ROM_IMAGE_SIZE=0x15800 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -43,7 +43,7 @@ # option ROM_IMAGE_SIZE=0x15800 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -67,8 +67,8 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" -#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/iwill/dk8s2/Config.lb =================================================================== --- trunk/coreboot-v2/targets/iwill/dk8s2/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/iwill/dk8s2/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -57,18 +57,18 @@ # ### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### #option FALLBACK_SIZE=524288 #option FALLBACK_SIZE=98304 option FALLBACK_SIZE=131072
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. option ROM_IMAGE_SIZE=65536
### -### Compute where this copy of linuxBIOS will start in the boot rom +### Compute where this copy of coreboot will start in the boot rom ### # ### @@ -80,7 +80,7 @@ option TTYS0_BAUD=115200
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately @@ -101,7 +101,7 @@
#
-## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM option _RAMBASE=0x004000
## @@ -117,7 +117,7 @@ # ### ### Compute the start location and size size of -### The linuxBIOS bootloader. +### The coreboot bootloader. ### option CONFIG_ROM_PAYLOAD = 1
@@ -128,7 +128,7 @@ # option ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM # option ROM_SIZE = 512*1024-48*1024-48*1024 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" option USE_FALLBACK_IMAGE=0 option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) option ROM_SECTION_OFFSET= 0 @@ -147,7 +147,7 @@ end
romimage "fallback" - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" option USE_FALLBACK_IMAGE=1 option ROM_SECTION_SIZE = FALLBACK_SIZE option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE) @@ -164,4 +164,4 @@ # payload /usr/src/filo-0.4.2/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/iwill/dk8x/Config.lb =================================================================== --- trunk/coreboot-v2/targets/iwill/dk8x/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/iwill/dk8x/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -57,18 +57,18 @@ # ### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### #option FALLBACK_SIZE=524288 #option FALLBACK_SIZE=98304 option FALLBACK_SIZE=131072
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. option ROM_IMAGE_SIZE=65536
### -### Compute where this copy of linuxBIOS will start in the boot rom +### Compute where this copy of coreboot will start in the boot rom ### # ### @@ -80,7 +80,7 @@ option TTYS0_BAUD=115200
## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately @@ -101,7 +101,7 @@
#
-## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM option _RAMBASE=0x004000
## @@ -117,7 +117,7 @@ # ### ### Compute the start location and size size of -### The linuxBIOS bootloader. +### The coreboot bootloader. ### option CONFIG_ROM_PAYLOAD = 1
@@ -128,7 +128,7 @@ # option ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM # option ROM_SIZE = 512*1024-48*1024-48*1024 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" option USE_FALLBACK_IMAGE=0 option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) option ROM_SECTION_OFFSET= 0 @@ -147,7 +147,7 @@ end
romimage "fallback" - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" option USE_FALLBACK_IMAGE=1 option ROM_SECTION_SIZE = FALLBACK_SIZE option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE) @@ -164,4 +164,4 @@ # payload /usr/src/filo-0.4.2/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/lippert/frontrunner/Config.lb =================================================================== --- trunk/coreboot-v2/targets/lippert/frontrunner/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/lippert/frontrunner/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -9,7 +9,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x16000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi @@ -21,7 +21,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x16000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebia @@ -30,4 +30,4 @@ payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/momentum/apache/Config.lb =================================================================== --- trunk/coreboot-v2/targets/momentum/apache/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/momentum/apache/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -16,13 +16,13 @@ ## Exception vectors (other than reset vector) option _EXCEPTION_VECTORS=_RESET+0x100
- ## Start of linuxBIOS in the boot rom + ## Start of coreboot in the boot rom ## = _RESET + exeception vector table size option _ROMSTART=_RESET+0x3100
- ## LinuxBIOS C code runs at this location in RAM + ## Coreboot C code runs at this location in RAM option _RAMBASE=0x00100000 option _RAMSTART=0x00100000 end
-buildrom ./linuxbios.rom ROM_SIZE "normal" +buildrom ./coreboot.rom ROM_SIZE "normal"
Modified: trunk/coreboot-v2/targets/motorola/sandpoint/Config.lb =================================================================== --- trunk/coreboot-v2/targets/motorola/sandpoint/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/motorola/sandpoint/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -17,15 +17,15 @@ ## Exception vectors (other than reset vector) option _EXCEPTION_VECTORS=_RESET+0x100
- ## Start of linuxBIOS in the boot rom + ## Start of coreboot in the boot rom ## = _RESET + exeception vector table size option _ROMSTART=_RESET+0x3100
- ## LinuxBIOS C code runs at this location in RAM + ## Coreboot C code runs at this location in RAM option _RAMBASE=0x00100000 option _RAMSTART=0x00100000
option CONFIG_SANDPOINT_ALTIMUS=1 end
-buildrom ./linuxbios.rom ROM_SIZE "normal" +buildrom ./coreboot.rom ROM_SIZE "normal"
Modified: trunk/coreboot-v2/targets/motorola/sandpoint/Config.lb.ide_stream =================================================================== --- trunk/coreboot-v2/targets/motorola/sandpoint/Config.lb.ide_stream 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/motorola/sandpoint/Config.lb.ide_stream 2008-01-18 15:08:58 UTC (rev 3053) @@ -74,11 +74,11 @@ ## Exception vectors (other than reset vector) option _EXCEPTION_VECTORS=_RESET+0x100
- ## Start of linuxBIOS in the boot rom + ## Start of coreboot in the boot rom ## = _RESET + exeception vector table size option _ROMSTART=_RESET+0x3100
- ## LinuxBIOS C code runs at this location in RAM + ## Coreboot C code runs at this location in RAM option _RAMBASE=0x00100000 option _RAMSTART=0x00100000
@@ -87,4 +87,4 @@ mainboard motorola/sandpoint end
-buildrom ./linuxbios.rom ROM_SIZE "normal" +buildrom ./coreboot.rom ROM_SIZE "normal"
Modified: trunk/coreboot-v2/targets/msi/ms6178/Config.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms6178/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/msi/ms6178/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -37,14 +37,14 @@
romimage "normal" option USE_FALLBACK_IMAGE = 0 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/msi/ms7260/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms7260/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/msi/ms7260/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -28,7 +28,7 @@ option USE_FALLBACK_IMAGE = 0 option ROM_IMAGE_SIZE = 128 * 1024 option XIP_ROM_SIZE = 256 * 1024 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload __PAYLOAD__ end
@@ -37,7 +37,7 @@ option USE_FALLBACK_IMAGE = 1 option ROM_IMAGE_SIZE = 128 * 1024 option XIP_ROM_SIZE = 256 * 1024 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload __PAYLOAD__ end
@@ -46,8 +46,8 @@ option USE_FALLBACK_IMAGE = 0 option ROM_IMAGE_SIZE = FAILOVER_SIZE option XIP_ROM_SIZE = FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION = ".0Failover" + option COREBOOT_EXTRA_VERSION = ".0Failover" end
-# buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" +# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
Modified: trunk/coreboot-v2/targets/msi/ms7260/Config.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms7260/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/msi/ms7260/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -31,7 +31,7 @@ option USE_FALLBACK_IMAGE = 0 option ROM_IMAGE_SIZE = 128 * 1024 option XIP_ROM_SIZE = 256 * 1024 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end
@@ -40,7 +40,7 @@ option USE_FALLBACK_IMAGE = 1 option ROM_IMAGE_SIZE = 128 * 1024 option XIP_ROM_SIZE = 256 * 1024 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end
@@ -49,8 +49,8 @@ option USE_FALLBACK_IMAGE = 0 option ROM_IMAGE_SIZE = FAILOVER_SIZE option XIP_ROM_SIZE = FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION = ".0Failover" + option COREBOOT_EXTRA_VERSION = ".0Failover" end
-# buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" +# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
Modified: trunk/coreboot-v2/targets/msi/ms9185/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms9185/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/msi/ms9185/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -12,14 +12,14 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE = 96 * 1024 - option LINUXBIOS_EXTRA_VERSION=".0-normal" + option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end
romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE = 96 * 1024 - option LINUXBIOS_EXTRA_VERSION=".0-fallback" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/msi/ms9185/Config.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms9185/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/msi/ms9185/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -40,7 +40,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -68,7 +68,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf
Modified: trunk/coreboot-v2/targets/msi/ms9282/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms9282/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/msi/ms9282/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -12,14 +12,14 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE = 96 * 1024 - option LINUXBIOS_EXTRA_VERSION=".0-normal" + option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end
romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE = 96 * 1024 - option LINUXBIOS_EXTRA_VERSION=".0-fallback" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/msi/ms9282/Config.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms9282/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/msi/ms9282/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -37,7 +37,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -65,7 +65,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf
Modified: trunk/coreboot-v2/targets/newisys/khepri/Config.lb =================================================================== --- trunk/coreboot-v2/targets/newisys/khepri/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/newisys/khepri/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -25,20 +25,20 @@
option FALLBACK_SIZE=131072
-## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM option _RAMBASE=0x00004000
romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="-Khepri-Normal" + option COREBOOT_EXTRA_VERSION="-Khepri-Normal" payload ../../../payloads/tg3--ide_disk.zelf end
romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="-Khepri-Fallback" + option COREBOOT_EXTRA_VERSION="-Khepri-Fallback" payload ../../../payloads/tg3--ide_disk.zelf end
Modified: trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -27,7 +27,7 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION=".0-Normal" + option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end
@@ -35,8 +35,8 @@ option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION=".0-Fallback" + option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config.lb =================================================================== --- trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -43,7 +43,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -71,7 +71,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -101,8 +101,8 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
Modified: trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config.lb.kernel =================================================================== --- trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config.lb.kernel 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config.lb.kernel 2008-01-18 15:08:58 UTC (rev 3053) @@ -39,7 +39,7 @@ # option ROM_IMAGE_SIZE=0x15800 # option ROM_IMAGE_SIZE=0x13800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -71,9 +71,9 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" "failover" -#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/olpc/btest/Config.lb =================================================================== --- trunk/coreboot-v2/targets/olpc/btest/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/olpc/btest/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -3,7 +3,7 @@ target btest mainboard olpc/btest
-# Don't let LinuxBIOS compress the payload +# Don't let coreboot compress the payload #option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 #option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 #option CONFIG_PRECOMPRESSED_PAYLOAD=0 @@ -17,8 +17,8 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=32*1024 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" payload /tmp/olpcpayload.elf end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback"
Modified: trunk/coreboot-v2/targets/olpc/rev_a/Config.1M.lb =================================================================== --- trunk/coreboot-v2/targets/olpc/rev_a/Config.1M.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/olpc/rev_a/Config.1M.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -3,7 +3,7 @@ target rev_a_1M mainboard olpc/rev_a
-# Don't let LinuxBIOS compress the payload +# Don't let coreboot compress the payload # option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 #option CONFIG_PRECOMPRESSED_PAYLOAD=1
@@ -16,8 +16,8 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=32*1024 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" payload /tmp/olpcpayload.elf end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback"
Modified: trunk/coreboot-v2/targets/olpc/rev_a/Config.SPI.lb =================================================================== --- trunk/coreboot-v2/targets/olpc/rev_a/Config.SPI.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/olpc/rev_a/Config.SPI.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -3,7 +3,7 @@ target rev_a_1M mainboard olpc/rev_a
-# Don't let LinuxBIOS compress the payload +# Don't let coreboot compress the payload #option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 #option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 #option CONFIG_PRECOMPRESSED_PAYLOAD=0 @@ -17,8 +17,8 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=32*1024 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" payload /tmp/olpcpayload.elf end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback"
Modified: trunk/coreboot-v2/targets/olpc/rev_a/Config.kernel.lb =================================================================== --- trunk/coreboot-v2/targets/olpc/rev_a/Config.kernel.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/olpc/rev_a/Config.kernel.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -9,7 +9,7 @@ #romimage "normal" # option USE_FALLBACK_IMAGE=0 # option ROM_IMAGE_SIZE=0x10000 -# option LINUXBIOS_EXTRA_VERSION=".0Normal" +# option COREBOOT_EXTRA_VERSION=".0Normal" ## payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf ## payload ../../../../tg3--ide_disk.zelf ## payload ../../../../../lnxieepro100.ebi @@ -21,7 +21,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebia @@ -31,5 +31,5 @@ payload /tmp/olpc end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" -#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/olpc/rev_a/Config.lb =================================================================== --- trunk/coreboot-v2/targets/olpc/rev_a/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/olpc/rev_a/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -13,8 +13,8 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=32*1024 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" payload /tmp/olpcpayload.elf end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback"
Modified: trunk/coreboot-v2/targets/pcengines/alix1c/Config.lb =================================================================== --- trunk/coreboot-v2/targets/pcengines/alix1c/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/pcengines/alix1c/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -3,11 +3,11 @@
option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use +## ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). Leave 36k for VSA. option ROM_SIZE = (512 * 1024) - (36 * 1024)
-## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image, +## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, ## not including any payload. option ROM_IMAGE_SIZE = (64 * 1024)
@@ -18,8 +18,8 @@
romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload ../payload.elf end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback"
Modified: trunk/coreboot-v2/targets/sunw/ultra40/Config.lb =================================================================== --- trunk/coreboot-v2/targets/sunw/ultra40/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/sunw/ultra40/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -23,7 +23,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x17800 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -52,7 +52,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x17800 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -70,4 +70,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -13,7 +13,7 @@ option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x18000 - option LINUXBIOS_EXTRA_VERSION=".0-normal" + option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end
@@ -21,7 +21,7 @@ option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x18000 - option LINUXBIOS_EXTRA_VERSION=".0-fallback" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end
@@ -30,7 +30,7 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION=".0-failover" + option COREBOOT_EXTRA_VERSION=".0-failover" end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
Modified: trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb =================================================================== --- trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -38,7 +38,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -66,7 +66,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -96,8 +96,8 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
Modified: trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb.kernel =================================================================== --- trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb.kernel 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb.kernel 2008-01-18 15:08:58 UTC (rev 3053) @@ -35,7 +35,7 @@ # option ROM_IMAGE_SIZE=0x15800 # option ROM_IMAGE_SIZE=0x13800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -67,9 +67,9 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" "failover" -#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -14,8 +14,8 @@ option USE_FALLBACK_IMAGE=1 # option ROM_IMAGE_SIZE=32 * 1024 # 0x8000 option ROM_IMAGE_SIZE=128 * 1024 # 0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" payload __PAYLOAD__ end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback"
Modified: trunk/coreboot-v2/targets/technologic/ts5300/Config.lb =================================================================== --- trunk/coreboot-v2/targets/technologic/ts5300/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/technologic/ts5300/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -11,7 +11,7 @@ #romimage "normal" # option USE_FALLBACK_IMAGE=0 # option ROM_IMAGE_SIZE=0x10000 -# option LINUXBIOS_EXTRA_VERSION=".0-Normal" +# option COREBOOT_EXTRA_VERSION=".0-Normal" # payload /etc/hosts #end
@@ -24,8 +24,8 @@ # option ROM_IMAGE_SIZE=48 * 1024 # 0x8000 # option ROM_IMAGE_SIZE=64 * 1024 # 0x10000 # option ROM_IMAGE_SIZE=512 * 1024 # 0x10000 -# option LINUXBIOS_EXTRA_VERSION=".0-Fallback" - option LINUXBIOS_EXTRA_VERSION=".0" +# option COREBOOT_EXTRA_VERSION=".0-Fallback" + option COREBOOT_EXTRA_VERSION=".0" payload /home/stepan/filo-ts5300.elf end
Modified: trunk/coreboot-v2/targets/totalimpact/briq/Config.lb =================================================================== --- trunk/coreboot-v2/targets/totalimpact/briq/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/totalimpact/briq/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -42,11 +42,11 @@ ## Exception vectors (other than reset vector) option _EXCEPTION_VECTORS=_RESET+0x100
- ## Start of linuxBIOS in the boot rom + ## Start of coreboot in the boot rom ## = _RESET + exeception vector table size option _ROMSTART=_RESET+0x3100
- ## LinuxBIOS C code runs at this location in RAM + ## Coreboot C code runs at this location in RAM option _RAMBASE=0x00100000 option _RAMSTART=0x00100000
@@ -55,4 +55,4 @@
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" +buildrom ./coreboot.rom ROM_SIZE "normal"
Modified: trunk/coreboot-v2/targets/tyan/s1846/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s1846/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s1846/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -38,14 +38,14 @@
romimage "normal" option USE_FALLBACK_IMAGE = 0 - option LINUXBIOS_EXTRA_VERSION = ".0Normal" + option COREBOOT_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + option COREBOOT_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s2735/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2735/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2735/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -16,7 +16,7 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x11800 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -31,7 +31,7 @@ option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x11800 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -42,4 +42,4 @@ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s2735/ns2735 =================================================================== --- trunk/coreboot-v2/targets/tyan/s2735/ns2735 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2735/ns2735 2008-01-18 15:08:58 UTC (rev 3053) @@ -2,7 +2,7 @@ TYANMB=s2735 cd "$TYANMB" make -#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -#cat ../fwx.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -cp -f $TYANMB"_linuxbios.rom" /home/yhlu/ +#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +#cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +cp -f $TYANMB"_coreboot.rom" /home/yhlu/
Modified: trunk/coreboot-v2/targets/tyan/s2850/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2850/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2850/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -20,7 +20,7 @@ # option ROM_IMAGE_SIZE=0x13c00 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -43,7 +43,7 @@ # option ROM_IMAGE_SIZE=0x13c00 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -58,4 +58,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s2850/ns2850 =================================================================== --- trunk/coreboot-v2/targets/tyan/s2850/ns2850 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2850/ns2850 2008-01-18 15:08:58 UTC (rev 3053) @@ -2,6 +2,6 @@ TYANMB=s2850 cd "$TYANMB" make -cat ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -#cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -#cp -f $TYANMB"_linuxbios.rom" /home/yhlu/ +cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +#cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +#cp -f $TYANMB"_coreboot.rom" /home/yhlu/
Modified: trunk/coreboot-v2/targets/tyan/s2875/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2875/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2875/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -20,7 +20,7 @@ # option ROM_IMAGE_SIZE=0x17800 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -42,7 +42,7 @@ # option ROM_IMAGE_SIZE=0x17800 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -56,4 +56,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s2875/ns2875 =================================================================== --- trunk/coreboot-v2/targets/tyan/s2875/ns2875 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2875/ns2875 2008-01-18 15:08:58 UTC (rev 3053) @@ -2,5 +2,5 @@ TYANMB=s2875 cd "$TYANMB" make -cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -cp -f $TYANMB"_linuxbios.rom" /home/yhlu/ +cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +cp -f $TYANMB"_coreboot.rom" /home/yhlu/
Modified: trunk/coreboot-v2/targets/tyan/s2880/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2880/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2880/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -20,7 +20,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x17800 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -42,7 +42,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x17800 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -56,4 +56,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s2880/ns2880 =================================================================== --- trunk/coreboot-v2/targets/tyan/s2880/ns2880 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2880/ns2880 2008-01-18 15:08:58 UTC (rev 3053) @@ -2,7 +2,7 @@ TYANMB=s2880 cd "$TYANMB" make -#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -#cat ../fwx.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -cp -f $TYANMB"_linuxbios.rom" /home/yhlu/ +#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +#cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +cp -f $TYANMB"_coreboot.rom" /home/yhlu/
Modified: trunk/coreboot-v2/targets/tyan/s2881/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2881/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2881/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -19,7 +19,7 @@ # option ROM_IMAGE_SIZE=0x16000 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -40,7 +40,7 @@ # option ROM_IMAGE_SIZE=0x16000 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -54,4 +54,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s2881/ns2881 =================================================================== --- trunk/coreboot-v2/targets/tyan/s2881/ns2881 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2881/ns2881 2008-01-18 15:08:58 UTC (rev 3053) @@ -2,7 +2,7 @@ TYANMB=s2881 cd "$TYANMB" make -#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -cat ../fwx.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -#cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -cp -f $TYANMB"_linuxbios.rom" /home/yhlu/ +#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +#cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +cp -f $TYANMB"_coreboot.rom" /home/yhlu/
Modified: trunk/coreboot-v2/targets/tyan/s2882/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2882/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2882/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -18,7 +18,7 @@ # option ROM_IMAGE_SIZE=0x16000 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -36,7 +36,7 @@ # option ROM_IMAGE_SIZE=0x16000 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -48,4 +48,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s2882/ns2882 =================================================================== --- trunk/coreboot-v2/targets/tyan/s2882/ns2882 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2882/ns2882 2008-01-18 15:08:58 UTC (rev 3053) @@ -2,7 +2,7 @@ TYANMB=s2882 cd "$TYANMB" make -#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -#cat ../fwx.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -cp -f $TYANMB"_linuxbios.rom" /home/yhlu/ +#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +#cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +cp -f $TYANMB"_coreboot.rom" /home/yhlu/
Modified: trunk/coreboot-v2/targets/tyan/s2885/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2885/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2885/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -19,7 +19,7 @@ # option ROM_IMAGE_SIZE=0x16200 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -43,7 +43,7 @@ # option ROM_IMAGE_SIZE=0x16200 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -60,4 +60,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s2885/ns2885 =================================================================== --- trunk/coreboot-v2/targets/tyan/s2885/ns2885 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2885/ns2885 2008-01-18 15:08:58 UTC (rev 3053) @@ -2,5 +2,5 @@ TYANMB=s2885 cd "$TYANMB" make -cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -cp -f $TYANMB"_linuxbios.rom" /home/yhlu/ +cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +cp -f $TYANMB"_coreboot.rom" /home/yhlu/
Modified: trunk/coreboot-v2/targets/tyan/s2891/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2891/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2891/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -21,7 +21,7 @@ # option ROM_IMAGE_SIZE=0x16000 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -43,7 +43,7 @@ # option ROM_IMAGE_SIZE=0x16000 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -58,4 +58,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s2891/Config.lb.com2 =================================================================== --- trunk/coreboot-v2/targets/tyan/s2891/Config.lb.com2 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2891/Config.lb.com2 2008-01-18 15:08:58 UTC (rev 3053) @@ -18,7 +18,7 @@ # option ROM_IMAGE_SIZE=0x13000 option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -39,7 +39,7 @@ # option ROM_IMAGE_SIZE=0x13000 option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -54,4 +54,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s2892/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2892/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2892/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -22,7 +22,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x17800 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -44,7 +44,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x17800 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -58,4 +58,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s2895/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2895/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2895/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -23,7 +23,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x17800 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -53,7 +53,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x17800 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -76,9 +76,9 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" -#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -27,7 +27,7 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION=".0-Normal" + option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end
@@ -35,8 +35,8 @@ option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION=".0-Fallback" + option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s2912/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2912/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2912/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -41,7 +41,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -69,7 +69,7 @@ option ROM_IMAGE_SIZE=0x20000 # option ROM_IMAGE_SIZE=0x15800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -99,8 +99,8 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
Modified: trunk/coreboot-v2/targets/tyan/s2912/Config.lb.kernel =================================================================== --- trunk/coreboot-v2/targets/tyan/s2912/Config.lb.kernel 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s2912/Config.lb.kernel 2008-01-18 15:08:58 UTC (rev 3053) @@ -37,7 +37,7 @@ # option ROM_IMAGE_SIZE=0x15800 # option ROM_IMAGE_SIZE=0x13800 option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -69,9 +69,9 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=FAILOVER_SIZE option XIP_ROM_SIZE=FAILOVER_SIZE - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" "failover" -#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" +#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s4880/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s4880/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s4880/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -18,7 +18,7 @@ # option ROM_IMAGE_SIZE=0x19c00 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -37,7 +37,7 @@ # option ROM_IMAGE_SIZE=0x19c00 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -50,4 +50,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s4880/ns4880 =================================================================== --- trunk/coreboot-v2/targets/tyan/s4880/ns4880 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s4880/ns4880 2008-01-18 15:08:58 UTC (rev 3053) @@ -2,7 +2,7 @@ TYANMB=s4880 cd "$TYANMB" make -#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -cat ../fwx.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -#cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -cp -f $TYANMB"_linuxbios.rom" /home/yhlu/ +#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +#cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +cp -f $TYANMB"_coreboot.rom" /home/yhlu/
Modified: trunk/coreboot-v2/targets/tyan/s4882/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s4882/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s4882/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -20,7 +20,7 @@ # option ROM_IMAGE_SIZE=0x16200 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -43,7 +43,7 @@ # option ROM_IMAGE_SIZE=0x16200 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../payloads/tg3--ide_disk.zelf # payload ../../../payloads/filo.elf # payload ../../../payloads/filo_mem.elf @@ -58,4 +58,4 @@ # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/tyan/s4882/ns4882 =================================================================== --- trunk/coreboot-v2/targets/tyan/s4882/ns4882 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/tyan/s4882/ns4882 2008-01-18 15:08:58 UTC (rev 3053) @@ -2,7 +2,7 @@ TYANMB=s4882 cd "$TYANMB" make -#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -cat ../fwx.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -#cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom" -cp -f $TYANMB"_linuxbios.rom" /home/yhlu/ +#cat ../fwx.rom ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +cat ../fwx.rom ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +#cat ./normal/coreboot.rom ./fallback/coreboot.rom > $TYANMB"_coreboot.rom" +cp -f $TYANMB"_coreboot.rom" /home/yhlu/
Modified: trunk/coreboot-v2/targets/via/epia/Config.512kflash.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia/Config.512kflash.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/via/epia/Config.512kflash.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -11,7 +11,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf payload ../../../../../lnxieepro100.ebi @@ -20,10 +20,10 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf payload ../../../../../lnxieepro100.ebi end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/via/epia/Config.512kflash.linuxtiny.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia/Config.512kflash.linuxtiny.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/via/epia/Config.512kflash.linuxtiny.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -12,10 +12,10 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=64*1024 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf payload /tmp/linux.elf end
-buildrom ./linuxbios.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback"
Modified: trunk/coreboot-v2/targets/via/epia/Config.filo.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia/Config.filo.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/via/epia/Config.filo.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -9,7 +9,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi @@ -19,11 +19,11 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/via/epia/Config.ituner.filo.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia/Config.ituner.filo.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/via/epia/Config.ituner.filo.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -11,7 +11,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi @@ -21,11 +21,11 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi payload /tmp/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/via/epia/Config.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/via/epia/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -15,7 +15,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi @@ -25,11 +25,11 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi payload /etc/hosts end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/via/epia-m/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia-m/Config-abuild.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/via/epia-m/Config-abuild.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -17,11 +17,11 @@
### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### option FALLBACK_SIZE=131072
-## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM option _RAMBASE=0x00004000
# @@ -30,15 +30,15 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=64*1024 - option LINUXBIOS_EXTRA_VERSION=".0-Normal" + option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end
romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=64*1024 - option LINUXBIOS_EXTRA_VERSION=".0-Fallback" + option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/via/epia-m/Config.512kflash.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia-m/Config.512kflash.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/via/epia-m/Config.512kflash.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -18,17 +18,17 @@
### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### option FALLBACK_SIZE=131072
-## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM option _RAMBASE=0x00004000
# ### ### Compute the start location and size size of -### The linuxBIOS bootloader. +### The coreboot bootloader. ###
# @@ -37,7 +37,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf payload ../../../../../lnxieepro100.ebi @@ -46,10 +46,10 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf payload ../../../../../lnxieepro100.ebi end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/via/epia-m/Config.etherboot.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia-m/Config.etherboot.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/via/epia-m/Config.etherboot.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -17,17 +17,17 @@
### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### option FALLBACK_SIZE=131072
-## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM option _RAMBASE=0x00004000
# ### ### Compute the start location and size size of -### The linuxBIOS bootloader. +### The coreboot bootloader. ###
# @@ -36,7 +36,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf payload ../../../../../lnxieepro100.ebi @@ -45,10 +45,10 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf payload ../../../../../lnxieepro100.ebi end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/via/epia-m/Config.filo.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia-m/Config.filo.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/via/epia-m/Config.filo.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -17,17 +17,17 @@
### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### option FALLBACK_SIZE=131072
-## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM option _RAMBASE=0x00004000
# ### ### Compute the start location and size size of -### The linuxBIOS bootloader. +### The coreboot bootloader. ###
# @@ -36,7 +36,7 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Normal" + option COREBOOT_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi @@ -46,11 +46,11 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + option COREBOOT_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi payload ../../../../../../filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/via/epia-m/Config.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia-m/Config.lb 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/via/epia-m/Config.lb 2008-01-18 15:08:58 UTC (rev 3053) @@ -19,11 +19,11 @@
### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### option FALLBACK_SIZE=131072
-## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM option _RAMBASE=0x00004000
# @@ -33,7 +33,7 @@ option USE_FALLBACK_IMAGE=0 #option ROM_IMAGE_SIZE=128*1024 option ROM_IMAGE_SIZE=64*1024 - option LINUXBIOS_EXTRA_VERSION=".0-Normal" + option COREBOOT_EXTRA_VERSION=".0-Normal" payload $(HOME)/svn/payload.elf end
@@ -41,8 +41,8 @@ option USE_FALLBACK_IMAGE=1 #option ROM_IMAGE_SIZE=128*1024 option ROM_IMAGE_SIZE=60*1024 - option LINUXBIOS_EXTRA_VERSION=".0-Fallback" + option COREBOOT_EXTRA_VERSION=".0-Fallback" payload $(HOME)/svn/payload.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/targets/via/epia-m/Config.vga.filo =================================================================== --- trunk/coreboot-v2/targets/via/epia-m/Config.vga.filo 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/targets/via/epia-m/Config.vga.filo 2008-01-18 15:08:58 UTC (rev 3053) @@ -16,16 +16,16 @@
### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### option FALLBACK_SIZE=0x18000
-## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM option _RAMBASE=0x00004000
### ### Compute the start location and size size of -### The linuxBIOS bootloader. +### The coreboot bootloader. ###
# @@ -36,15 +36,15 @@ option ROM_IMAGE_SIZE=0xc000 option ROM_SECTION_OFFSET=0x10000 option ROM_SECTION_SIZE=0x18000 - option LINUXBIOS_EXTRA_VERSION=".0-Normal" + option COREBOOT_EXTRA_VERSION=".0-Normal" payload $(HOME)/svn/filo.elf end
romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0xc000 - option LINUXBIOS_EXTRA_VERSION=".0-Fallback" + option COREBOOT_EXTRA_VERSION=".0-Fallback" payload $(HOME)/svn/filo.elf end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
Modified: trunk/coreboot-v2/util/ADLO/CAST =================================================================== --- trunk/coreboot-v2/util/ADLO/CAST 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/ADLO/CAST 2008-01-18 15:08:58 UTC (rev 3053) @@ -6,4 +6,4 @@ Boch's bios related issues. Thanks!
I also got tips from Eric W. Biederman, as well as other members of the -LinuxBIOS mailing list. +coreboot mailing list.
Modified: trunk/coreboot-v2/util/ADLO/HACKING =================================================================== --- trunk/coreboot-v2/util/ADLO/HACKING 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/ADLO/HACKING 2008-01-18 15:08:58 UTC (rev 3053) @@ -6,7 +6,7 @@ the bochs mainline.
thus when designing an patch for rombios.c both needs of - linuxbios as well as bochs needed to be taken into + coreboot as well as bochs needed to be taken into consideration.
- there are motherboard specific code in loader.s. until this issue
Modified: trunk/coreboot-v2/util/ADLO/INSTALL =================================================================== --- trunk/coreboot-v2/util/ADLO/INSTALL 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/ADLO/INSTALL 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,4 +1,4 @@ -1) Are you familar with LinuxBIOS? +1) Are you familar with coreboot?
no : abort yes: go to next step. @@ -41,7 +41,7 @@
make
-9) use the resulting elf "payload" file with LinuxBIOS as you would +9) use the resulting elf "payload" file with coreboot as you would have used any other elf file. For example put it on the same - EERPOM as LinuxBIOS is, or use EtherBOOT to load the payload + EERPOM as coreboot is, or use EtherBOOT to load the payload file from hdd or network.
Modified: trunk/coreboot-v2/util/ADLO/README =================================================================== --- trunk/coreboot-v2/util/ADLO/README 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/ADLO/README 2008-01-18 15:08:58 UTC (rev 3053) @@ -4,7 +4,7 @@
ADLO
- A project to combine LinuxBIOS and BOCHS BIOS to add support + A project to combine coreboot and BOCHS BIOS to add support for booting legacy applications, such as Microsoft Windows.
========================================== @@ -12,13 +12,13 @@ Boot Overvew: ADLO requires an boot loader with ELF support. - In our case it is either LinuxBIOS or EtherBOOT. + In our case it is either coreboot or EtherBOOT.
Sample execution paths:
-LinuxBIOS -> ADLO -> LILO -> LINUX +coreboot -> ADLO -> LILO -> LINUX
-LinuxBIOS -> EtherBOOT -> ADLO -> LILO -> LINUX +coreboot -> EtherBOOT -> ADLO -> LILO -> LINUX
Then it can start any real mode application. In our case it could be LILO or GRUB, but @@ -56,7 +56,7 @@ select device to boot set memory for Int15/EAX=E820 enable LBA - copy LinuxBIOS table [TODO] + copy coreboot table [TODO] -shadow : enable/write/read -copy: @@ -177,11 +177,11 @@ Environment overview
ADLO is an ELF file and thus can be loaded either directly from 1) -LinuxBIOS, or 2) via EtherBOOT, or 3) via EtherBOOT+ AA patch for FS +coreboot, or 2) via EtherBOOT, or 3) via EtherBOOT+ AA patch for FS support.
1) -Both LinuxBIOS and ADLO are on the same EEPROM chip. From end-user +Both coreboot and ADLO are on the same EEPROM chip. From end-user viewpoint it is probably the most similar to the bios classic. (computer boots up and just loads whatever is in MBR).
@@ -201,15 +201,15 @@ ADLO requires an boot loader with ELF support. In our case it is:
- -LinuxBIOS - -LinuxBIOS and EtherBOOT - -LinuxBIOS and EtherBOOT + AA polled I/O patch (w/ FS support). + -coreboot + -coreboot and EtherBOOT + -coreboot and EtherBOOT + AA polled I/O patch (w/ FS support).
- As little as LinuxBIOS only is required to get ADLO + As little as coreboot only is required to get ADLO up and running.
For development purposes it is recommended full set of - LinuxBIOS + EtherBOOT and boot via DHCP/TFTP. + coreboot + EtherBOOT and boot via DHCP/TFTP. ------------------------------------------
Modified: trunk/coreboot-v2/util/ADLO/STATUS =================================================================== --- trunk/coreboot-v2/util/ADLO/STATUS 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/ADLO/STATUS 2008-01-18 15:08:58 UTC (rev 3053) @@ -128,7 +128,7 @@ fix bios to properly handle reboot
setup PIRQ table for P6STMT mbo. - have it extract from linuxbios somehow.. + have it extract from coreboot somehow.. find it in ram and copy...
hack gcc to support 16 bit real mode.
Modified: trunk/coreboot-v2/util/ADLO/bochs/bios/rombios.c =================================================================== --- trunk/coreboot-v2/util/ADLO/bochs/bios/rombios.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/ADLO/bochs/bios/rombios.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -144,7 +144,7 @@ //#define BX_PCIBIOS 1 #define BX_APM 0
-#define LINUXBIOS 1 +#define COREBOOT 1
#define BX_USE_ATADRV 1 //#define BX_ELTORITO_BOOT 1 @@ -1633,12 +1633,12 @@ //-------------------------------------------------------------------------- // keyboard_init //-------------------------------------------------------------------------- -// this file is based on LinuxBIOS implementation of keyboard.c +// this file is based on coreboot implementation of keyboard.c // could convert to #asm to gain space void keyboard_init() { -#ifndef LINUXBIOS +#ifndef COREBOOT Bit16u max;
/* ------------------- Flush buffers ------------------------*/
Modified: trunk/coreboot-v2/util/ADLO/loader.s =================================================================== --- trunk/coreboot-v2/util/ADLO/loader.s 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/ADLO/loader.s 2008-01-18 15:08:58 UTC (rev 3053) @@ -9,7 +9,7 @@ ;***************************************************** ; A) setup GDT, so that we do not depend on program ; that loaded us for GDT. -; Ex: LinuxBIOS and EtherBOOT use different GDT's. +; Ex: coreboot and EtherBOOT use different GDT's.
;----------------------------------------------------- ; 0) @@ -90,7 +90,7 @@ nop nop ;***************************************************** -; X) copy -- LinuxBIOS table into safe place. +; X) copy -- coreboot table into safe place.
;; TODO. ;; Q1 : what is the size of table. @@ -188,7 +188,7 @@ ; 119mb = 0x77 00 00 00 ; (this is for 128mb of ram) ; (FIXME: this value is currently hard coded) -; (it should be being passed from LinuxBIOS ) +; (it should be being passed from coreboot )
; for WinFast 6300 ; 07 70 = 0770
Modified: trunk/coreboot-v2/util/abuild/abuild =================================================================== --- trunk/coreboot-v2/util/abuild/abuild 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/abuild/abuild 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,8 +1,8 @@ #!/bin/bash # -# LinuxBIOS autobuild +# coreboot autobuild # -# This script builds LinuxBIOS images for all available targets. +# This script builds coreboot images for all available targets. # # (C) 2004 by Stefan Reinauer stepan@openbios.org # (C) 2006 by coresystems GmbH info@coresystems.de @@ -18,7 +18,7 @@ ABUILD_VERSION="0.4"
# Where shall we place all the build trees? -TARGET=$( pwd )/linuxbios-builds +TARGET=$( pwd )/coreboot-builds XMLFILE=$( pwd )/abuild.xml
# path to payload. Should be more generic @@ -27,7 +27,7 @@ # Lines of error context to be printed in FAILURE case CONTEXT=5
-TESTSUBMISSION="http://qa.linuxbios.org/deployment/send.php" +TESTSUBMISSION="http://qa.coreboot.org/deployment/send.php"
# One might want to adjust these in case of cross compiling MAKE="make" @@ -143,25 +143,25 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x17000 - option LINUXBIOS_EXTRA_VERSION=".0-normal" + option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end
romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x17000 - option LINUXBIOS_EXTRA_VERSION=".0-fallback" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" EOF else cat <<EOF romimage "only" - option LINUXBIOS_EXTRA_VERSION=".0" + option COREBOOT_EXTRA_VERSION=".0" payload __PAYLOAD__ end -buildrom ./linuxbios.rom ROM_SIZE "only" +buildrom ./coreboot.rom ROM_SIZE "only" EOF fi ) > $TARGET/Config-${VENDOR}_${MAINBOARD}.lb @@ -403,7 +403,7 @@ fi
# image does not exist. we silently skip the patch. - if [ ! -r "$TARGET/${VENDOR}_${MAINBOARD}/linuxbios.rom" ]; then + if [ ! -r "$TARGET/${VENDOR}_${MAINBOARD}/coreboot.rom" ]; then return 0 fi
@@ -422,9 +422,9 @@
printf "Submitting image for board $VENDOR $MAINBOARD to test system...\n"
- curl -f -F "romfile=@$TARGET/${VENDOR}_${MAINBOARD}/linuxbios.rom" \ + curl -f -F "romfile=@$TARGET/${VENDOR}_${MAINBOARD}/coreboot.rom" \ -F "mode=abuild" -F "mainboard=${VENDOR}_${MAINBOARD}" -F "submit=Upload" \ - "http://qa.linuxbios.org/deployment/send.php" + "http://qa.coreboot.org/deployment/send.php"
printf "\n" return 0 @@ -447,7 +447,7 @@ printf " [-x|--xml] write xml log file \n" printf " (defaults to $XMLFILE)\n" printf " [-T|--test] submit image(s) to automated test system\n" - printf " [lbroot] absolute path to LinuxBIOS sources\n" + printf " [lbroot] absolute path to coreboot sources\n" printf " (defaults to $LBROOT)\n\n" }
@@ -455,10 +455,10 @@ { cat << EOF
-LinuxBIOS autobuild v$ABUILD_VERSION ($ABUILD_DATE) +coreboot autobuild v$ABUILD_VERSION ($ABUILD_DATE)
Copyright (C) 2004 by Stefan Reinauer stepan@openbios.org -Copyright (C) 2006 by coresystems GmbH info@coresystems.de +Copyright (C) 2006-2008 by coresystems GmbH info@coresystems.de
This program is free software; you may redistribute it under the terms of the GNU General Public License. This program has absolutely no
Modified: trunk/coreboot-v2/util/abuild/abuild.1 =================================================================== --- trunk/coreboot-v2/util/abuild/abuild.1 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/abuild/abuild.1 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,25 +1,25 @@ .TH ABUILD 1 "October 24, 2006" .SH NAME -abuild - build LinuxBIOS images for all available targets +abuild - build coreboot images for all available targets .SH SYNOPSIS .B abuild \fR[\fB-abxVh\fR] [\fB-t\fR vendor/board] [\fB-p\fR dir] [LBROOT] .SH DESCRIPTION .B abuild -is a utility used to easily build LinuxBIOS images for all available targets. +is a utility used to easily build coreboot images for all available targets. .SH OPTIONS The .B "[LBROOT]" parameter tells .B abuild -where the root directory of the LinuxBIOS build tree resides. Per default +where the root directory of the coreboot build tree resides. Per default this is .B "../.." as the .B abuild script resides in -.BR "[LBROOT]/utils/abuild" . +.BR "[CBROOT]/utils/abuild" . .TP .B "-a, --all" Build previously succeeded ports as well. @@ -45,7 +45,7 @@ .B "-T, --test" Submit generated image(s) to the automated test system. The results of the tests will be made available at -.B http://qa.linuxbios.org/log_manual.php +.B http://qa.coreboot.org/log_manual.php .TP .B "-v, --verbose" More verbose output. @@ -56,7 +56,7 @@ .B "-V, --version" Show version information and exit. .SH BUGS -Please report any bugs at http://tracker.linuxbios.org/. +Please report any bugs at http://tracker.coreboot.org/. .SH LICENCE .B abuild is covered by the GNU General Public License (GPL), version 2 or later.
Modified: trunk/coreboot-v2/util/analysis/Makefile =================================================================== --- trunk/coreboot-v2/util/analysis/Makefile 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/analysis/Makefile 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,4 +1,4 @@ -# LinuxBIOS codebase analysis tool +# Coreboot codebase analysis tool # # This makefile collects source usage information for all working targets. # @@ -38,7 +38,7 @@ analysis.dat: analysis.txt @ echo Writing gnuplot data file ($@). @ echo -e > $@ "# gnuplot dataset auto-generated $(shell date)" \ - "\nset title "LinuxBIOS Codebase Analysis"" \ + "\nset title "Coreboot Codebase Analysis"" \ "\nset style data boxes" \ "\nset style fill solid .5" \ $(foreach target, $(TARGETS), "\n"set label "$(target)" at $(words $(labels))$(eval labels += $(target)),-145 rotate front) \
Modified: trunk/coreboot-v2/util/buildrom/buildrom.c =================================================================== --- trunk/coreboot-v2/util/buildrom/buildrom.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/buildrom/buildrom.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -20,7 +20,7 @@ void usage() { fprintf(stderr, "Usage: buildrom <input> <output> <payload> "); - fprintf(stderr, " <linuxbios-size> <total-size>\n"); + fprintf(stderr, " <coreboot-size> <total-size>\n"); exit(1); }
@@ -57,22 +57,22 @@ if (fstat(infd, &inbuf) < 0) fatal("stat of infile"); if (inbuf.st_size > size) { - fprintf(stderr, "linuxbios image is %d bytes; only %d allowed\n", + fprintf(stderr, "coreboot image is %d bytes; only %d allowed\n", (int)inbuf.st_size, size); - fatal("Linuxbios input file larger than allowed size!\n"); + fatal("Coreboot input file larger than allowed size!\n"); }
if (fstat(payloadfd, &payloadbuf) < 0) fatal("stat of infile"); if (payloadbuf.st_size > (romsize - size)){ - fprintf(stderr, "ERROR: payload (%d) + linuxbios (%d) - Size is %d bytes larger than ROM size (%d).\n", + fprintf(stderr, "ERROR: payload (%d) + coreboot (%d) - Size is %d bytes larger than ROM size (%d).\n", payloadbuf.st_size, size, payloadbuf.st_size+size-romsize, romsize); exit(1); }
- printf("Payload: %d LinuxBIOS: %d ROM size: %d Left space: %d\n", + printf("Payload: %d coreboot: %d ROM size: %d Left space: %d\n", payloadbuf.st_size, size, romsize, romsize-payloadbuf.st_size-size);
Modified: trunk/coreboot-v2/util/lbtdump/README =================================================================== --- trunk/coreboot-v2/util/lbtdump/README 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/lbtdump/README 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,7 +1,7 @@
-lbtdump is a utility to dump the LinuxBIOS table +lbtdump is a utility to dump the coreboot table to a human readable form.
This needs to be run as root (or setuid) on a system -running LinuxBIOS. +running coreboot.
Modified: trunk/coreboot-v2/util/lbtdump/lbtdump.c =================================================================== --- trunk/coreboot-v2/util/lbtdump/lbtdump.c 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/lbtdump/lbtdump.c 2008-01-18 15:08:58 UTC (rev 3053) @@ -94,7 +94,7 @@ head->table_checksum); continue; } - fprintf(stdout, "Found LinuxBIOS table at: %08lx\n", addr); + fprintf(stdout, "Found coreboot table at: %08lx\n", addr); return head;
}; @@ -303,7 +303,7 @@ rec = (struct lb_record *)(((char *)head) + head->header_bytes); last = (struct lb_record *)(((char *)rec) + head->table_bytes);
- printf("LinuxBIOS header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n", + printf("Coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n", head->header_bytes, head->header_checksum, head->table_bytes, head->table_checksum, head->table_entries); print_lb_records(rec, last, addr + head->header_bytes);
Modified: trunk/coreboot-v2/util/newconfig/config.g =================================================================== --- trunk/coreboot-v2/util/newconfig/config.g 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/newconfig/config.g 2008-01-18 15:08:58 UTC (rev 3053) @@ -200,7 +200,7 @@ # -----------------------------------------------------------------------------
class romimage: - """A rom image is the ultimate goal of linuxbios""" + """A rom image is the ultimate goal of coreboot""" def __init__ (self, name): # name of this rom image self.name = name @@ -1995,7 +1995,7 @@ writemakefileheader(file, makefilepath)
# main rule - file.write("\nall: linuxbios.rom\n\n") + file.write("\nall: coreboot.rom\n\n") file.write(".PHONY: all\n\n") #file.write("include cpuflags\n") # Putting "include cpuflags" in the Makefile has the problem that the @@ -2122,7 +2122,7 @@ for genfile in ['Makefile', 'nsuperio.c', 'static.c', - 'LinuxBIOSDoc.config' ]: + 'corebootDoc.config' ]: file.write("GENERATED += %s\n" % genfile) file.write("GENERATED += %s\n" % image.getincludefilename())
@@ -2156,9 +2156,9 @@ file.write("\n\n") file.write("include Makefile.settings\n\n") for i, o in romimages.items(): - file.write("%s/linuxbios.rom:\n" % o.getname()) + file.write("%s/coreboot.rom:\n" % o.getname()) file.write("\tif (cd %s; \\n" % o.getname()) - file.write("\t\tmake linuxbios.rom)\\n") + file.write("\t\tmake coreboot.rom)\\n") file.write("\tthen true; else exit 1; fi;\n\n") file.write("clean: ") for i in romimages.keys(): @@ -2171,11 +2171,11 @@ for i in buildroms: file.write("%s:" % i.name) for j in i.roms: - file.write(" %s/linuxbios.rom " % j) + file.write(" %s/coreboot.rom " % j) file.write("\n") file.write("\t cat ") for j in i.roms: - file.write(" %s/linuxbios.rom " % j) + file.write(" %s/coreboot.rom " % j) file.write("> %s\n\n" %i.name)
@@ -2183,7 +2183,7 @@ for i in romimages.keys(): file.write(" %s-clean" % i) for i, o in romimages.items(): - file.write(" %s/linuxbios.rom" % o.getname()) + file.write(" %s/coreboot.rom" % o.getname()) file.write("\n\n")
writemakefilefooter(file, makefilepath) @@ -2304,7 +2304,7 @@ if __name__=='__main__': from sys import argv if (len(argv) < 3): - fatal("Args: <file> <path to linuxbios>") + fatal("Args: <file> <path to coreboot>")
top_config_file = os.path.abspath(sys.argv[1])
Modified: trunk/coreboot-v2/util/optionlist/Options-wiki.xsl =================================================================== --- trunk/coreboot-v2/util/optionlist/Options-wiki.xsl 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/optionlist/Options-wiki.xsl 2008-01-18 15:08:58 UTC (rev 3053) @@ -25,7 +25,7 @@ indent="yes" />
<xsl:template match="/"> -This is an automatically generated list of '''LinuxBIOS compile-time options'''. +This is an automatically generated list of '''coreboot compile-time options'''.
Last update: <xsl:value-of select="//creationdate"/>.
Modified: trunk/coreboot-v2/util/optionlist/Options.xsl =================================================================== --- trunk/coreboot-v2/util/optionlist/Options.xsl 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/optionlist/Options.xsl 2008-01-18 15:08:58 UTC (rev 3053) @@ -43,11 +43,11 @@ <xsl:template match="/"> <html> <head> -<title>LinuxBIOS Options</title> +<title>Coreboot Options</title> </head> <body> -<h2>LinuxBIOS Options</h2> -<p>This is an automatically generated list of LinuxBIOS compile time +<h2>Coreboot Options</h2> +<p>This is an automatically generated list of coreboot compile time options. Created at <xsl:value-of select="//creationdate"/>.</p> <table border="1"> <tr bgcolor="#0975a7">
Modified: trunk/coreboot-v2/util/optionlist/README =================================================================== --- trunk/coreboot-v2/util/optionlist/README 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/optionlist/README 2008-01-18 15:08:58 UTC (rev 3053) @@ -1,4 +1,4 @@ -I would like to contribute the following to the LinuxBIOS wiki in case +I would like to contribute the following to the coreboot wiki in case it's useable:
1. I have written a rather small Python script to convert the Options.lb
Modified: trunk/coreboot-v2/util/optionlist/mkOptionList.py =================================================================== --- trunk/coreboot-v2/util/optionlist/mkOptionList.py 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/optionlist/mkOptionList.py 2008-01-18 15:08:58 UTC (rev 3053) @@ -106,7 +106,7 @@ input = prepInput(input) output = parseInput(input) - print "mkOptionList.py: LinuxBIOS option list generator" + print "mkOptionList.py: coreboot option list generator" print " input file : ", inFilename print " output file: ", outFilename
Modified: trunk/coreboot-v2/util/romcc/romcc.1 =================================================================== --- trunk/coreboot-v2/util/romcc/romcc.1 2008-01-18 10:35:56 UTC (rev 3052) +++ trunk/coreboot-v2/util/romcc/romcc.1 2008-01-18 15:08:58 UTC (rev 3053) @@ -10,8 +10,8 @@ is a C compiler which produces binaries which do not rely on RAM, but instead only use CPU registers. .PP -It is prominently used in the LinuxBIOS project to compile C code which -needs to run before the (Linux)BIOS has initialized the RAM, but can be +It is prominently used in the coreboot project to compile C code which +needs to run before the firmware has initialized the RAM, but can be used for other purposes, too. .SH OPTIONS .TP
-
svn＠coreboot.org