Re: [coreboot] Debugging MRC issues with FPS

[Zoran Stojsavljevic]

Hello Stephanie,

With all due respect, you do realize that Coreboot.org is on your side,
INTEL embedded side of the business, correct? Coreboot.org is trying to
help debugging these issues, because in the past there were several
attempts to determine INTEL FSP MRC problems. And number of Coreboot.org
developers on different INTEL platforms ran on undocumented POST FSP codes.
We had here these discussions in the past.

I do not see any obstacles why INTEL should NOT post (in public domain) FSP
POST codes, well documented.

Stephanie, you do realize setbacks in business cases, considering
competition: AMD and ARM?

Please, could you reconsider your/INTEL decision?!

Thank you,
Zoran

On Tue, Sep 27, 2016 at 12:09 AM, Wang, Stephanie 
wrote:
> Hello
>
> Thank you for your interest in Intel® FSP!  coreboot.org is not the right
> forum for FSP questions. Intel has no plan to post FSP binary or MRC post
> code to coreboot.org. Please take this question to Intel IPS.
>
> Thanks
>
> Stephanie
>
> *From:* Zoran Stojsavljevic [mailto:[e-mail]]
> *Sent:* Sunday, September 25, 2016 11:48 AM
> *To:* Adolfo Sanchez 
> *Cc:* [e-mail]; Yang, York ; Wang,
> Stephanie ; Mahesh, Divya <
> [e-mail]>
> *Subject:* Re: [coreboot] Debugging MRC issues with FPS
>
> Hello Adolfo (you are somehow known to me, isn't it that you are working
> for INTEL Inside support, or maybe not)!? What does it mean _cr in your
> email address (Costa Rica, isn't it)?! ;-)
>
> Let us ask this very relevant people in INTEL Inside, who MANDATORY should
> know info you are asking, since they are responsible, aren't they (INTEL
> insider is asking for FSP POST codes Coreboot outsiders, which will again
> ask much more relevant INTEL Insiders)??? IN -> OUT -> IN schema. Shouldn't
> it be: IN -> IN schema ONLY??? :-))
>
> Verrückt (Deutsche Sprache)?! :LOL:
>
> Hello Stephanie,
>
> You realize how this all strange is (the context)? *BTW, we, Coreboot
> members... We should once forever know these POST codes are (you hide
> inside FSPs - probably reminiscence of BIOS MRC post codes, or you tell us
> all?!)? Could you, please, make this as public info to INTEL Outside?*
>
> Divya,
>
> Could you, please, arrange what I am (in *RED*) asking for (INTEL Inside
> and INTEL Outside)? You do realize why I am asking this, correct???💡
>
> (don't touch/blame Adolfo... You should ask many questions somewhere
> else... You know exactly where!)
>
> Thank you,
>
> Zoran Stojsavljevic, independent FREE contributor
>
> On Sun, Sep 25, 2016 at 5:55 PM, Adolfo Sanchez 
> wrote:
>
> Hello
>
> I would like to know the best way to get information about a Failure
> related with Memory Initialization when using FPS.
>
> Specially when the FSPmemoryinit is being called but then the system
> hangs. POST Code 0x50
>
> What flags can be enable to get more information?
>
> Best Regards,
>
> Adolfo Sanchez