[commit] r5396 - in trunk/src: cpu/x86/mtrr mainboard/tyan/s2895 northbridge/amd/amdk8 southbridge/nvidia/ck804 superio/smsc/lpc47b397

[repository service]

Author: stepan
Date: Fri Apr  9 16:46:51 2010
New Revision: 5396
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5396

Log:
zero warnings days.

The tyan s2895 is down to 3 warnings, 2 of which are caused by #warning.

The 1000 ways of how the AMD code waits for the cores to be started up 
are a real pain for the brain.

Signed-off-by: Stefan Reinauer 
Acked-by: Stefan Reinauer

Modified:
   trunk/src/cpu/x86/mtrr/earlymtrr.c
   trunk/src/mainboard/tyan/s2895/romstage.c
   trunk/src/northbridge/amd/amdk8/debug.c
   trunk/src/northbridge/amd/amdk8/incoherent_ht.c
   trunk/src/northbridge/amd/amdk8/northbridge.c
   trunk/src/northbridge/amd/amdk8/raminit.c
   trunk/src/northbridge/amd/amdk8/raminit.h
   trunk/src/northbridge/amd/amdk8/setup_resource_map.c
   trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c
   trunk/src/southbridge/nvidia/ck804/ck804_smbus.h
   trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c

Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c
==============================================================================
--- trunk/src/cpu/x86/mtrr/earlymtrr.c	Fri Apr  9 15:49:48 2010	(r5395)
+++ trunk/src/cpu/x86/mtrr/earlymtrr.c	Fri Apr  9 16:46:51 2010	(r5396)
@@ -97,7 +97,7 @@
    
 }

-static void early_mtrr_init(void)
+static inline void early_mtrr_init(void)
 {
    static const unsigned long mtrr_msrs[] = {
    	/* fixed mtrr */

Modified: trunk/src/mainboard/tyan/s2895/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/romstage.c	Fri Apr  9 15:49:48 2010	(r5395)
+++ trunk/src/mainboard/tyan/s2895/romstage.c	Fri Apr  9 16:46:51 2010	(r5396)
@@ -15,35 +15,26 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-
 #include "pc80/serial.c"
 #include "console/console.c"
 #include "lib/ramtest.c"
-
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-
 #define SUPERIO_GPIO_IO_BASE 0x400
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/debug.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-
+#include <cpu/amd/mtrr.h>
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)

static void memreset_setup(void)
@@ -54,15 +45,14 @@
 {
 }

-static void sio_gpio_setup(void){
-
+static void sio_gpio_setup(void)
+{
    unsigned value;

/*Enable onboard scsi*/
    lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
    value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
    lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
-
 }

static inline void activate_spd_rom(const struct mem_controller *ctrl)
@@ -111,10 +101,9 @@

static void sio_setup(void)
 {
-
    unsigned value;
-	uint32_t dword;
-	uint8_t byte;
+	u32 dword;
+	u8 byte;

pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);

@@ -134,18 +123,15 @@
    value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
    value &= 0xbf;
    lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
-
 }

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	static const uint16_t spd_addr [] = {
+	static const u16 spd_addr [] = {
    	(0xa<<3)|0, (0xa<<3)|2, 0, 0,
    	(0xa<<3)|1, (0xa<<3)|3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
    	(0xa<<3)|4, (0xa<<3)|6, 0, 0,
    	(0xa<<3)|5, (0xa<<3)|7, 0, 0,
-#endif
    };

int needs_reset;
@@ -170,8 +156,6 @@
    	bsp_apicid = init_cpus(cpu_init_detectedx);
    }

-//	post_code(0x32);
-
    lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
    uart_init();
    console_init();
@@ -186,11 +170,10 @@
    needs_reset = setup_coherent_ht_domain();

wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+
    // It is said that we should start core1 after all core0 launched
    start_other_cores();
    wait_all_other_cores_started(bsp_apicid);
-#endif

needs_reset |= ht_setup_chains_x();

Modified: trunk/src/northbridge/amd/amdk8/debug.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/debug.c	Fri Apr  9 15:49:48 2010	(r5395)
+++ trunk/src/northbridge/amd/amdk8/debug.c	Fri Apr  9 16:46:51 2010	(r5396)
@@ -84,7 +84,7 @@
 }
 #endif

-static void dump_pci_devices(void)
+static inline void dump_pci_devices(void)
 {
    device_t dev;
    for(dev = PCI_DEV(0, 0, 0);

Modified: trunk/src/northbridge/amd/amdk8/incoherent_ht.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/incoherent_ht.c	Fri Apr  9 15:49:48 2010	(r5395)
+++ trunk/src/northbridge/amd/amdk8/incoherent_ht.c	Fri Apr  9 16:46:51 2010	(r5396)
@@ -476,6 +476,7 @@

}

+#if 0
 #if RAMINIT_SYSINFO == 1
 static void ht_setup_chain(device_t udev, unsigned upos, struct sys_info *sysinfo)
 #else
@@ -506,6 +507,8 @@
    return ht_setup_chainx(udev, upos, 0, offset_unitid);
 #endif
 }
+#endif
+
 static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val)
 {
    uint32_t dword, dword_old;

Modified: trunk/src/northbridge/amd/amdk8/northbridge.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/northbridge.c	Fri Apr  9 15:49:48 2010	(r5395)
+++ trunk/src/northbridge/amd/amdk8/northbridge.c	Fri Apr  9 16:46:51 2010	(r5396)
@@ -925,7 +925,7 @@

#if 1
 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
-	/* Round the mmio hold to 64M */
+	/* Round the mmio hole to 64M */
    mmio_basek &= ~((64*1024) - 1);
 #endif

Modified: trunk/src/northbridge/amd/amdk8/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit.c	Fri Apr  9 15:49:48 2010	(r5395)
+++ trunk/src/northbridge/amd/amdk8/raminit.c	Fri Apr  9 16:46:51 2010	(r5396)
@@ -7,6 +7,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
 #include <stdlib.h>
+#include <reset.h>
 #include "raminit.h"
 #include "amdk8.h"

@@ -564,11 +565,13 @@

static int is_opteron(const struct mem_controller *ctrl)
 {
-	/* Test to see if I am an Opteron.
-	 * FIXME Socket 939 based Athlon64 have dual channel capability,
-	 * too, so we need a better test for Opterons
+	/* Test to see if I am an Opteron.  Socket 939 based Athlon64
+	 * have dual channel capability, too, so we need a better test
+	 * for Opterons. 
+	 * However, all code uses is_opteron() to find out whether to
+	 * use dual channel, so if we really check for opteron here, we
+	 * need to fix up all code using this function, too.
     */
-#warning "FIXME: Implement a better test for Opterons"
    uint32_t nbcap;
    nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
    return !!(nbcap & NBCAP_128Bit);

Modified: trunk/src/northbridge/amd/amdk8/raminit.h
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit.h	Fri Apr  9 15:49:48 2010	(r5395)
+++ trunk/src/northbridge/amd/amdk8/raminit.h	Fri Apr  9 16:46:51 2010	(r5396)
@@ -11,4 +11,10 @@
    uint16_t channel1[DIMM_SOCKETS];
 };

+#if defined(__PRE_RAM__) && defined(RAMINIT_SYSINFO) && RAMINIT_SYSINFO == 1
+void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo);
+#else
+void sdram_initialize(int controllers, const struct mem_controller *ctrl);
+#endif
+
 #endif /* RAMINIT_H */

Modified: trunk/src/northbridge/amd/amdk8/setup_resource_map.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/setup_resource_map.c	Fri Apr  9 15:49:48 2010	(r5395)
+++ trunk/src/northbridge/amd/amdk8/setup_resource_map.c	Fri Apr  9 16:46:51 2010	(r5396)
@@ -3,15 +3,14 @@
 static void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base)
 {
    int i;
-//      print_debug("setting up resource map offset....");
-#if 0
-	print_debug("\n");
+#if RES_DEBUG
+	printk(BIOS_DEBUG, "setting up resource map offset....\n");
 #endif
    for(i = 0; i < max; i += 3) {
    	device_t dev;
    	unsigned where;
    	unsigned long reg;
-#if 0
+#if RES_DEBUG
    	prink_debug("%08x <- %08x\n", register_values[i] +  offset_pci_dev, register_values[i+2]);
 #endif
    	dev = (register_values[i] & ~0xfff) + offset_pci_dev;
@@ -27,7 +26,9 @@
    	pci_write_config32(register_values[i], reg);
 #endif
    }
-//      print_debug("done.\n");
+#if RES_DEBUG
+	printk(BIOS_DEBUG, "done.\n");
+#endif
 }

#define RES_PCI_IO 0x10
@@ -40,12 +41,7 @@
    int i;

#if RES_DEBUG
-	print_debug("setting up resource map ex offset....");
-
-#endif
-
-#if RES_DEBUG
-	print_debug("\n");
+	printk(BIOS_DEBUG, "setting up resource map ex offset....\n");
 #endif
    for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
@@ -112,21 +108,19 @@
    }

#if RES_DEBUG
-	print_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 #endif
 }
+
+#if defined(SOUTHBRIDGE_NVIDIA_MCP55) || defined(SOUTHBRIDGE_NVIDIA_CK804)
 static void setup_resource_map_x(const unsigned int *register_values, int max)
 {
    int i;

#if RES_DEBUG
-	print_debug("setting up resource map ex offset....");
-
+	printk(BIOS_DEBUG, "setting up resource map ex....\n");
 #endif

-#if RES_DEBUG
-	print_debug("\n");
-#endif
    for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
    	printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
@@ -188,47 +182,12 @@
    }

#if RES_DEBUG
-	print_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 #endif
 }
-
-#if 0
-static void setup_iob_resource_map(const unsigned int *register_values, int max)
-{
-	int i;
-
-	for(i = 0; i < max; i += 3) {
-		unsigned where;
-		unsigned reg;
-
-		where = register_values[i];
-#if 0
-		udelay(2000);
-		print_debug_hex16(where);
-#endif
-		reg = inb(where);
-#if 0
-		print_debug("=");
-		print_debug_hex8(reg);
 #endif

-		reg &= register_values[i+1];
-		reg |= register_values[i+2];
 #if 0
-		print_debug(" <-  ");
-		print_debug_hex8(reg);
-#endif
-		outb(reg, where);
-#if 0
-
-		print_debug(" -> ");
-		reg = inb(where);
-		print_debug_hex8(reg);
-		print_debug("\n");
-#endif
-	}
-}
-
 static void setup_io_resource_map(const unsigned int *register_values, int max)
 {
    int i;
@@ -240,30 +199,26 @@
    	where = register_values[i];
 #if 0
    	udelay(2000);
-		print_debug_hex16(where);
+		printk(BIOS_DEBUG, "%04x", where);
 #endif

reg = inl(where);
 #if 0
    	udelay(2000);
-		print_debug("=");
-		print_debug_hex32(reg);
+		printk(BIOS_DEBUG, "=%08x", reg);
 #endif
    	reg &= register_values[i+1];
    	reg |= register_values[i+2];

#if 0
    	udelay(2000);
-		print_debug(" <-  ");
-		print_debug_hex32(reg);
+		printk(BIOS_DEBUG, " <-  %08x", reg);
 #endif
    	outl(reg, where);
 #if 0
    	udelay(2000);
-		print_debug(" -> ");
    	reg = inl(where);
-		print_debug_hex32(reg);
-		print_debug("\n");
+		printk(BIOS_DEBUG, " ->  %08x\n", reg);
 #endif
    }
 }
@@ -276,9 +231,8 @@
    	unsigned where;
    	unsigned long reg;
 #if 0
-		print_debug_hex32(register_values[i]);
-		print_debug(" <-");
-		print_debug_hex32(register_values[i+2]);
+		prink(BIOS_DEBUG, "%08x <-  %08x\n", 
+			register_values[i], register_values[i+2]);
 #endif
    	where = register_values[i];
    	reg = read32(where);
@@ -286,10 +240,8 @@
    	reg |= register_values[i+2];
    	write32( where, reg);
 #if 0
-		print_debug(" RB ");
    	reg = read32(where);
-		print_debug_hex32(reg);
-		print_debug("\n");
+		prink(BIOS_DEBUG, " RB %08x\n", reg);
 #endif
    }
 }

Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c	Fri Apr  9 15:49:48 2010	(r5395)
+++ trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c	Fri Apr  9 16:46:51 2010	(r5396)
@@ -31,7 +31,7 @@
    return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }

-static int smbus_write_byte(unsigned device, unsigned address,
+static inline int smbus_write_byte(unsigned device, unsigned address,
    		    unsigned char val)
 {
    return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);

Modified: trunk/src/southbridge/nvidia/ck804/ck804_smbus.h
==============================================================================
--- trunk/src/southbridge/nvidia/ck804/ck804_smbus.h	Fri Apr  9 15:49:48 2010	(r5395)
+++ trunk/src/southbridge/nvidia/ck804/ck804_smbus.h	Fri Apr  9 16:46:51 2010	(r5396)
@@ -23,6 +23,8 @@
    outb(0x80, 0x80);
 }

+#if 0
+/* Not needed, upon write to PRTCL, the status will be auto-cleared. */
 static int smbus_wait_until_ready(unsigned smbus_io_base)
 {
    unsigned long loops;
@@ -38,6 +40,7 @@
    } while (--loops);
    return -2;
 }
+#endif

static int smbus_wait_until_done(unsigned smbus_io_base)
 {
@@ -53,6 +56,7 @@
    return -3;
 }

+#ifndef __PRE_RAM__
 static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
 {
    unsigned char global_status_register, byte;
@@ -129,6 +133,7 @@

return 0;
 }
+#endif

static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
    		      unsigned address)

Modified: trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c
==============================================================================
--- trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c	Fri Apr  9 15:49:48 2010	(r5395)
+++ trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c	Fri Apr  9 16:46:51 2010	(r5396)
@@ -30,6 +30,7 @@
    return inb(iobase+offset);
 }

+#if 0
 /* for GP60-GP64, GP66-GP85 */
 #define LPC47B397_GPIO_CNTL_INDEX 0x70
 #define LPC47B397_GPIO_CNTL_DATA 0x71
@@ -45,3 +46,4 @@
    outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX);
    return inb(iobase+LPC47B397_GPIO_CNTL_DATA);
 }
+#endif