I'm working with the LPC dongle by Artec to emulate boot flash. It works fine when controlling the processor via JTAG. That is when we debug the boot code under the JTAG control everything is ok (irq13=1 to stop the processor boot). When I disconnect the JTAG debugger and set irq13 to 0 to let the processor to boot from the LPC dongle flash, it does not boot. Do I need to perform other operations to let it boot autonomously?
TIA, llandre
DAVE Electronics System House - R&D Department web: http://www.dave.eu email: r&d2@dave-tech.it
On Wed, May 21, 2008 at 12:08:16PM +0200, llandre wrote:
I'm working with the LPC dongle by Artec to emulate boot flash.
..
When I disconnect the JTAG debugger and set irq13 to 0 to let the processor to boot from the LPC dongle flash, it does not boot. Do I need to perform other operations to let it boot autonomously?
No, it should work without changes.
But how do you provide power to the dongle?
Note that the dongle uses an Altera FPGA with the logic definition stored in an external flash memory, this flash memory is read by the FPGA on power up. There's also a power-up delay for the FPGA.
In total the dongle needs a few 100 ms to boot. The Geode needs to read from the memory before that time, so if you don't power the Artec dongle externally (e.g. USB cable) you will not be able to boot from it.
//Peter
When I disconnect the JTAG debugger and set irq13 to 0 to let the processor to boot from the LPC dongle flash, it does not boot. Do I need to perform other operations to let it boot autonomously?
No, it should work without changes.
But how do you provide power to the dongle?
Note that the dongle uses an Altera FPGA with the logic definition stored in an external flash memory, this flash memory is read by the FPGA on power up. There's also a power-up delay for the FPGA.
In total the dongle needs a few 100 ms to boot. The Geode needs to read from the memory before that time, so if you don't power the Artec dongle externally (e.g. USB cable) you will not be able to boot from it.
My Artec dongle is powered externally via USB cable so, when processor tries to fetch boot code, FPGA should be already up and running. However I noted that R26 on dongle in not mounted thus RESET coming from processor board is not connected to the reset monitor. Is that ok?
On Wed, May 21, 2008 at 12:57:33PM +0200, llandre wrote:
When I disconnect the JTAG debugger and set irq13 to 0 to let the processor to boot from the LPC dongle flash, it does not boot. Do I need to perform other operations to let it boot autonomously?
No, it should work without changes.
But how do you provide power to the dongle?
My Artec dongle is powered externally via USB cable so, when processor tries to fetch boot code, FPGA should be already up and running. However I noted that R26 on dongle in not mounted thus RESET coming from processor board is not connected to the reset monitor. Is that ok?
Hm. I did have to reset the dongle manually after flashing it, but otherwise I did not have any reset issues.
//Peter
Ühel kenal päeval, K, 2008-05-21 kell 12:57, kirjutas llandre:
When I disconnect the JTAG debugger and set irq13 to 0 to let the processor to boot from the LPC dongle flash, it does not boot. Do I need to perform other operations to let it boot autonomously?
No, it should work without changes.
But how do you provide power to the dongle?
Note that the dongle uses an Altera FPGA with the logic definition stored in an external flash memory, this flash memory is read by the FPGA on power up. There's also a power-up delay for the FPGA.
In total the dongle needs a few 100 ms to boot. The Geode needs to read from the memory before that time, so if you don't power the Artec dongle externally (e.g. USB cable) you will not be able to boot from it.
My Artec dongle is powered externally via USB cable so, when processor tries to fetch boot code, FPGA should be already up and running. However I noted that R26 on dongle in not mounted thus RESET coming from processor board is not connected to the reset monitor. Is that ok?
That is fully intentional. When it was mounted, then Geode reset would also reset the dongle, which would proceed to reload the logic definition into the FPGA again, and not be done by the time the Geode needs to read from the memory. R26 being no-load means that you can power over LPC bus instead of USB (paying attention to JMP4) by powering on the Geode and then resetting the Geode, to cause another read, but this time with the dongle being ready for it from LPC power being available earlier and the logic already loaded to the FPGA.
Regards, Mart Raudsepp Artec Design LLC
-
llandre -
Mart Raudsepp -
Peter Stuge