Author: stepan Date: Tue Aug 17 13:08:31 2010 New Revision: 5713 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5713
Log: Add support for Gigabyte MA785GMT mainboard.
Details of the hardware configuration can be found at http://www.gigabyte.com/products/product-page.aspx?pid=3478
Brief configuration is: 1. CPU:Support for AM3 processors: AMD PhenomTM II processor/ AMD Athlon™ II processor 2. North Bridge: AMD 785G 3. South Bridge: AMD SB710 4: Super IO : ITE8718F
The mainboard has two bios flashchip. Coreboot ROM should be flashed into the M_BIOS (which means main bios).
Signed-off-by: Wang Qing Pei wangqingpei@gmail.com Acked-by: Stefan Reinauer stepan@coresystems.de
Added: trunk/src/mainboard/gigabyte/ma785gmt/ - copied from r5712, trunk/src/mainboard/amd/tilapia_fam10/ Deleted: trunk/src/mainboard/gigabyte/ma785gmt/mb_sysconf.h trunk/src/mainboard/gigabyte/ma785gmt/spd_addr.h Modified: trunk/src/mainboard/gigabyte/Kconfig trunk/src/mainboard/gigabyte/ma785gmt/Kconfig trunk/src/mainboard/gigabyte/ma785gmt/acpi_tables.c trunk/src/mainboard/gigabyte/ma785gmt/chip.h trunk/src/mainboard/gigabyte/ma785gmt/devicetree.cb trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl trunk/src/mainboard/gigabyte/ma785gmt/mainboard.c trunk/src/mainboard/gigabyte/ma785gmt/mptable.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
Modified: trunk/src/mainboard/gigabyte/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/Kconfig Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/Kconfig Tue Aug 17 13:08:31 2010 (r5713) @@ -25,6 +25,6 @@ source "src/mainboard/gigabyte/ga-6bxc/Kconfig" source "src/mainboard/gigabyte/ga-6bxe/Kconfig" source "src/mainboard/gigabyte/m57sli/Kconfig" - +source "src/mainboard/gigabyte/ma785gmt/Kconfig" endchoice
Modified: trunk/src/mainboard/gigabyte/ma785gmt/Kconfig ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/Kconfig Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma785gmt/Kconfig Tue Aug 17 13:08:31 2010 (r5713) @@ -1,5 +1,5 @@ -config BOARD_AMD_TILAPIA_FAM10 - bool "Tilapia (Fam10)" +config BOARD_GIGABYTE_GA785GMT + bool "MA785GMT" select ARCH_X86 select CPU_AMD_SOCKET_AM3 select NORTHBRIDGE_AMD_AMDFAM10 @@ -26,100 +26,100 @@
config MAINBOARD_DIR string - default amd/tilapia_fam10 - depends on BOARD_AMD_TILAPIA_FAM10 + default gigabyte/ma785gmt + depends on BOARD_GIGABYTE_GA785GMT
config APIC_ID_OFFSET hex default 0x0 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config MAINBOARD_PART_NUMBER string - default "Tilapia (Fam10)" - depends on BOARD_AMD_TILAPIA_FAM10 + default "Gigabyte GA785GMT" + depends on BOARD_GIGABYTE_GA785GMT
config HW_MEM_HOLE_SIZEK hex default 0x100000 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config MAX_CPUS int default 8 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config MAX_PHYSICAL_CPUS int default 2 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config HW_MEM_HOLE_SIZE_AUTO_INC bool default n - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config MEM_TRAIN_SEQ int default 2 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config SB_HT_CHAIN_ON_BUS0 int default 1 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config HT_CHAIN_END_UNITID_BASE hex default 0x1 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config HT_CHAIN_UNITID_BASE hex default 0x0 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config IRQ_SLOT_COUNT int default 11 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config AMD_UCODE_PATCH_FILE string default "mc_patch_010000b6.h" - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config RAMTOP hex default 0x2000000 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config HEAP_SIZE hex default 0xc0000 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config ACPI_SSDTX_NUM int default 0 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x3060 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0x1022 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config RAMBASE hex default 0x200000 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
config COMPRESS hex default 0 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_GA785GMT
Modified: trunk/src/mainboard/gigabyte/ma785gmt/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/acpi_tables.c Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma785gmt/acpi_tables.c Tue Aug 17 13:08:31 2010 (r5713) @@ -26,8 +26,6 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h>
-#include "mb_sysconf.h" - #define DUMP_ACPI_TABLES 0
#if DUMP_ACPI_TABLES == 1
Modified: trunk/src/mainboard/gigabyte/ma785gmt/chip.h ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/chip.h Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma785gmt/chip.h Tue Aug 17 13:08:31 2010 (r5713) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Wang Qing Pei wangqingpei@gmail.com * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +21,4 @@ extern struct chip_operations mainboard_ops;
struct mainboard_config { -// int fixup_scsi; -// int fixup_vga; };
Modified: trunk/src/mainboard/gigabyte/ma785gmt/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma785gmt/devicetree.cb Tue Aug 17 13:08:31 2010 (r5713) @@ -1,4 +1,4 @@ -# sample config for amd/tilapia_fam10 +# sample config for gigabyte ga785gmt chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on chip cpu/amd/socket_AM3 #L1 and DDR3 @@ -111,35 +111,7 @@ device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end -# device pci 00.5 on end end end #pci_domain #for node 32 to node 63 -# device pci_domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #pci_domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # hard reset -# device pnp 0.9 off end # mcp55 -# device pnp 0.a on end # GH ext table -# end end
Modified: trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl Tue Aug 17 13:08:31 2010 (r5713) @@ -22,8 +22,8 @@ "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "TILAPIA ", /* TABLE ID */ + "GIGA ", /* OEMID */ + "GA785GMT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */
Modified: trunk/src/mainboard/gigabyte/ma785gmt/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/mainboard.c Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma785gmt/mainboard.c Tue Aug 17 13:08:31 2010 (r5713) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Wang Qing Pei wangqingpei@gmail.com * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -48,6 +48,7 @@
void set_pcie_dereset(void); void set_pcie_reset(void); +int is_dev3_present(void);
void set_pcie_dereset() { @@ -100,34 +101,92 @@ pci_write_config16(sm_dev, 0x7e, word); }
-#if 0 /* TODO: */ -/******************************************************** -* tilapia uses SB700 GPIO8 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) + + +/* + * justify the dev3 is exist or not + */ +int is_dev3_present(void) +{ + u16 word; + device_t sm_dev; + + /* access the smbus extended register */ + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + + /* put the GPIO68 output to tristate */ + word = pci_read_config16(sm_dev, 0x7e); + word |= 1 << 6; + pci_write_config16(sm_dev, 0x7e,word); + + /* read the GPIO68 input status */ + word = pci_read_config16(sm_dev, 0x7e); + + if(word & (1 << 10)){ + /*not exist*/ + return 0; + }else{ + /*exist*/ + return 1; + } +} + + +/* + * set gpio40 gfx + */ +static void set_gpio40_gfx(void) { u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; +// u16 word; + u32 dword; + device_t sm_dev; + /* disable the GPIO40 as CLKREQ2# function */ + byte = pm_ioread(0xd3); + byte &= ~(1 << 7); + pm_iowrite(0xd3, byte); + + /* disable the GPIO40 as CLKREQ3# function */ + byte = pm_ioread(0xd4); + byte &= ~(1 << 0); + pm_iowrite(0xd4, byte); + + /* enable pull up for GPIO68 */ + byte = pm2_ioread(0xf1); + byte &= ~(1 << 4); + pm2_iowrite(0xf1, byte);
+ /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 4); /* Set Gpio8 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 4) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); + /*if the dev3 is present, set the gfx to 2x8 lanes*/ + /*otherwise set the gfx to 1x16 lanes*/ + if(is_dev3_present()){ + + printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n"); + /* when the gpio40 is configured as GPIO, this will enable the output */ + pci_write_config32(sm_dev, 0xf8, 0x4); + dword = pci_read_config32(sm_dev, 0xfc); + dword &= ~(1 << 10); + + /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* 1 :enable two x8 , 0 : master slot enable only */ + dword |= (1 << 26); + pci_write_config32(sm_dev, 0xfc, dword); + + }else{ + printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n"); + /* when the gpio40 is configured as GPIO, this will enable the output */ + pci_write_config32(sm_dev, 0xf8, 0x4); + dword = pci_read_config32(sm_dev, 0xfc); + dword &= ~(1 << 10); + + /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* 1 :enable two x8 , 0 : master slot enable only */ + dword &= ~(1 << 26); + pci_write_config32(sm_dev, 0xfc, dword); + } } -#endif
/* * set thermal config @@ -194,16 +253,16 @@ }
/************************************************* -* enable the dedicated function in tilapia board. +* enable the dedicated function in ma785gmt board. * This function called early than rs780_enable. *************************************************/ -static void tilapia_enable(device_t dev) +static void ma785gmt_enable(device_t dev) { /* Leave it for furture use. */ /* struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; */
- printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard Gigabyte ma785gmt Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1) msr_t msr, msr2; @@ -247,6 +306,7 @@ set_pcie_dereset(); /* get_ide_dma66(); */ set_thermal_config(); + set_gpio40_gfx(); }
int add_mainboard_resources(struct lb_memory *mem) @@ -264,6 +324,6 @@ }
struct chip_operations mainboard_ops = { - CHIP_NAME("AMD TILAPIA Mainboard") - .enable_dev = tilapia_enable, + CHIP_NAME("GIGABYTE MA785GMT Mainboard") + .enable_dev = ma785gmt_enable, };
Modified: trunk/src/mainboard/gigabyte/ma785gmt/mptable.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/mptable.c Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma785gmt/mptable.c Tue Aug 17 13:08:31 2010 (r5713) @@ -43,7 +43,7 @@ { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; - static const char productid[12] = "TILAPIA "; + static const char productid[12] = "MA785GMT "; struct mp_config_table *mc; int j;
Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Tue Aug 17 13:08:31 2010 (r5713) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Wang Qing Pei wangqingpei@gmail.com * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,10 +29,6 @@ //used by raminit #define QRANK_DIMM_SUPPORT 1
-//used by incoherent_ht -#define FAM10_SCAN_PCI_BUS 0 -#define FAM10_ALLOCATE_IO_RANGE 0 - //used by init_cpus and fidvid #define SET_FIDVID 1 #define SET_FIDVID_CORE_RANGE 0 @@ -95,7 +91,6 @@ #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c"
-//#include "spd_addr.h"
#define RC00 0 #define RC01 1 @@ -137,6 +132,7 @@ sb700_lpc_init();
it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + it8718f_disable_reboot(); uart_init(); console_init(); printk(BIOS_DEBUG, "\n");
repository service wrote:
+++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Tue Aug 17 13:08:31 2010 (r5713)
..
@@ -137,6 +132,7 @@ sb700_lpc_init();
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
- it8718f_disable_reboot(); uart_init(); console_init(); printk(BIOS_DEBUG, "\n");
I know this was from a different commit, but I think maybe this _disable_reboot function should be moved out from the southbridge code, since it is not really specific for the it8718f southbridge.
It is critical to add new code in the most appropriate place. It can be difficult to find sometimes, and may require some more changes around the coreboot code.
//Peter
-
Peter Stuge -
repository service