Hi Uwe,
On Sunday 27 May 2007 22:59, Uwe Hermann wrote:
On Sun, May 27, 2007 at 07:19:18PM +0200, Juergen Beisert wrote:
Hi,
find below my CAR implementation for the Geode GX1 processor. Tested on my Geode GX1 system. Comments are welcome.
Great, thanks!
Is this for v2 or v3 (or both?)
Use it whereever you want. It only depends on the symbols "_sstage0_1" and "_car_size". But you can replace them with static values.
I used it in v2, but only to test it, if it works without a working SDRAM controller. I was not able to change the buildsystem to use it as a real CAR implementation (the v2 build system is to confusing and there are to many dependencies I can't control because I do not understand them).
Can you please post a signed-off patch which puts this file in some directory + the surrounding code which is necessary to actually use it? I'm really eager to try it out on my ASI 5BLMP (== IGEL WinNET III)...
It was intended for v3, but I can't provide you a patch because I changed the way to build it in arch/x86. And Ron don't like this way. So my patch would not help.
/*
Just a minor thing: The usual "This file is part of the LinuxBIOS project." line is missing here.
:-) Because it is currently not at part of the LinuxBIOS project.
Copyright (C) 2007 Juergen Beisert juergen@kreuzholzen.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
.globl CacheAsRam
CacheAsRam:
Can we make this "cache_as_ram"? We should stick with the coding and naming guidelines as much as possible...
Its GPL. Do what you like to do.
Otherwise the patch is nice and short, but I won't pretend I understand it ;) Haven't read the GX1 datasheets, yet...
Its trivial: Read chapter "4.3.2.5 Cache Test Registers" - switch of cache - enable write back mode - fill the cache control data (as it does it by itself when it is enabled) - use it =8-)
Juergen