Dear all,
I was given a computer with an ASUS P5Q last December and have been using as my main machine since then. About 2 months ago I discovered that it is supported by coreboot so I thought it would be fun to experiment with it.
I ordered a usb programmer and a couple of EEPROM chips, followed the tutorial and shortly after was enjoying my new fast BIOS. (I have the P5Q variant from the P5QC family in the source code.)
I was conservative at first with the .config and then started experimenting a bit. So I came across a few problems. Not being sure what to emailed Angel Pons who was very kind in providing comments and recommending me to contact the mailing list.
So, here goes:
1) I configured coreboot so that the CMOS was used for configuration values. The test was to change the sata mode to Compatible. This made the board unbootable, not even reaching the Seabios message. The solution was to disable the CMOS battery for some seconds. I forgot to take a serial port log. The board has an ICH10R southbridge which is the consumer version that can also function as a RAID controller. The devices supported by the board are defined in the devicetree.cb file where the IDE device 1f.5 is explicitly switched off and that may be why the board did not boot. I did not investigate this further but the expectation here would be that the CMOS value could be used to decide how to configure the controllers.
2) I then decided to try out Windows XP but the Installation would stop with STOP: 0xA5 (0x11, 0x8, ... .. ., .... ). I could not figure it out... Then I used a usb pen with "Active Boot Disk 9.4" in it, based on WindowsPE / Windows7. For that I got STOP: 0xA5 (0x1000, 0x0, 0xFFFFFFF0, 0x400000) and that actually provided a clue.
I searched in the ACPI tables and found this in the x4x.asl file " // Integrated graphics 0:2.0 #include <drivers/intel/gma/acpi/non-pch.asl "
and this inside that file non-pch.asl file
" Device (GFX0) { Name (_ADR, 0x00020000)
OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) Field (GFXC, DWordAcc, NoLock, Preserve) { Offset (0x10), BAR0, 64, Offset (0xe4), ASLE, 32, Offset (0xfc), ASLS, 32, }
OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) Field (GFRG, DWordAcc, NoLock, Preserve) { Offset (0x61254), BCLV, 16, BCLM, 16, } "
However the GFX0 device does not exist as my Northbridge is a 82P45 which is a model without integrated graphics. The solution was to comment the "#include <drivers/intel/gma/acpi/non-pch.asl" out of the x4x.asl file. I decided to try Win XP again and it no longer displayed the Stop: 0xA5 message. "Active Boot disk" also ran without problems.
It does not seem correct to me for coreboot to assume that all the x4x northbridges have integrated graphics. Wouldn't it be better to have two versions of the asl file, one with and another without the GMA.
3) For the XP installation to proceed I needed the AHCI driver on diskette so I downloaded it from Intel. I use Linux from Scratch with XFCE as my main operating system but it as I tried to copy the files to diskette I realised that the Floppy was no longer showing in thunar. It was there with the ASUS BIOS, what could be wrong?
I added the etc/floppy0 = 4 option to the coreboot.rom image which brought the floppy to the SEABIOS boot menu and I could even boot DOS from there. That did not work.
So I though the problem was this issue in the devicetree.cb as I was also getting errors in the cbmem log.
chip superio/winbond/w83667hg-a # Super I/O device pnp 2e.0 on # FDC # Global registers irq 0x2a = 0x00 irq 0x2c = 0x22 irq 0x2d = 0x00 # Floppy io 0x60 = 0x3f0 irq 0xf0 = 0x0e
As we can see IRQ 0x70 = 0x06 and DRQ 0x74 = 0x02 are missing from the Floppy section.
But Linux could still not see or talk with the floppy drive. I eventually fixed it by adding this option to the linux command line: floppy=0,4,cmos
At this point I gave up on this problem and moved on. The Floppy is back in the thunar file manager. Angel suggested that the problem may be that there is no definition for the floppy drive in the ACPI tables.
... Lots of problems with bad sectors later I was able to continue with the XP installation. I stopped at the screen where I need to select a partition to install the system to and decided to continue later. The important thing here is that XP no longer bluescreens.
4) This one is more of an annoyance. My PS/2 mouse did not work. I was also seeing this message in the log: PNP: 002e.5 init w83667hg_a_init: Disable mouse controller.PNP: 002e.5 init finished in 3 msecs
I had a good look at the source code around the error message and concluded that I needed the [*] PS/2 keyboard init option enabled.
We have this in src/superio/winbond/w83667hg-a/superio.c " mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE);
if (!mouse_detected && !acpi_is_wakeup_s3()) { printk(BIOS_INFO, "%s: Disable mouse controller.", __func__); "
And we see this in src/drivers/pc80/pc/keyboard.c: " uint8_t pc_keyboard_init(uint8_t probe_aux) { u8 retries; u8 regval; enum cb_err err; uint8_t aux_dev_detected;
if (!CONFIG(DRIVERS_PS2_KEYBOARD)) return 0;
" So the function returns immediately and the probe for the mouse never happens with the option off.
This was not obvious by looking at the help, which only talks about keyboards and states it is not needed if you use seabios: │ Enable this option to initialize PS/2 keyboards found connected │ │ to the PS/2 port. │ │ │ │ Some payloads (eg, filo) require this option. Other payloads │ │ (eg, GRUB 2, SeaBIOS, Linux) do not require it. │ │ Initializing a PS/2 keyboard can take several hundred milliseconds. │ │ │ │ If you know you will only use a payload which does not require │ │ this option, then you can say N here to speed up boot time. │ │ Otherwise say Y.
Something is not quite right in the logic behind all of this. I guess "initialize PS/2 keyboards found connected" could be replaced with "initialize PS/2 keyboards and mice found connected."
5) None of the secondary payloads coreinfo, nvramcui and Memtest86+ worked for me. I managed to get Memtest86+ working by selecting the "Master" version but did not investigate any further.
6) I tried to follow the "coreboot Overview" in https://www.coreboot.org/Developer_Manual but found it difficult, the crt0_romcc_epilogue.inc for example does net exist in the source tree. Is there any other updated overview somewhere else?
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Angel Pons suggested that I had a look at part 2 of the tutorial so that I could start proposing changes for review. I may start doing that, free time allowing... I'm not a programmer by trade (never worked with git for example) but I know C and learning about the PC architecture has been an hobby for me in the last few years. Coreboot has been amazing for that but I still have a lot to learn.
I hope it's ok to report issues to the mailing list like this, apologies for the long email.
Regards, Eduardo Batalha