On Mon, Feb 9, 2009 at 1:18 PM, Marc Jones marcj303@gmail.com wrote:
On Sat, Feb 7, 2009 at 10:28 AM, Marc Jones marcj303@gmail.com wrote:
On Sat, Feb 7, 2009 at 4:05 AM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 06.02.2009 23:37, Marc Jones wrote:
Setup the MTRRs in stage1 so that memory and cache are available throughout stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF. It also sets all system memory to WriteBack cached and sets the ROM area to cached.
Signed-off-by: Marc Jones marcj303@gmail.com
Fixed the comment for clarity and the ROM size based on the config.
Marc
r1128