Author: oxygene Date: Thu Mar 18 17:18:58 2010 New Revision: 5257 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5257
Log: Remove fallback/normal handling in mainboards' romstage.c like r5255 did for failover/fallback/normal mainboards.
Signed-off-by: Patrick Georgi patrick.georgi@coresystems.de Acked-by: Myles Watson mylesgw@gmail.com
Deleted: trunk/src/arch/i386/lib/failover.c trunk/src/arch/i386/lib/failover.lds trunk/src/mainboard/amd/mahogany/cache_as_ram_auto.c Modified: trunk/src/arch/i386/Makefile.inc trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/dell/s1850/failover.c trunk/src/mainboard/emulation/qemu-x86/failover.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/intel/jarrell/failover.c trunk/src/mainboard/intel/xe7501devkit/failover.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/olpc/btest/failover.c trunk/src/mainboard/olpc/rev_a/failover.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/x6dai_g/failover.c trunk/src/mainboard/supermicro/x6dhe_g/failover.c trunk/src/mainboard/supermicro/x6dhe_g2/failover.c trunk/src/mainboard/supermicro/x6dhr_ig/failover.c trunk/src/mainboard/supermicro/x6dhr_ig2/failover.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/romstage.c trunk/src/mainboard/via/epia-m/failover.c trunk/src/mainboard/via/epia-n/failover.c
Modified: trunk/src/arch/i386/Makefile.inc ============================================================================== --- trunk/src/arch/i386/Makefile.inc Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/arch/i386/Makefile.inc Thu Mar 18 17:18:58 2010 (r5257) @@ -87,7 +87,6 @@ crt0s := ldscripts := ldscripts += $(src)/arch/i386/init/ldscript_fallback_cbfs.lb -ldscripts += $(src)/arch/i386/lib/failover.lds ifeq ($(CONFIG_BIG_BOOTBLOCK),y) crt0s += $(src)/cpu/x86/16bit/entry16.inc ldscripts += $(src)/cpu/x86/16bit/entry16.lds @@ -160,12 +159,6 @@ ldscripts += $(src)/cpu/x86/car/cache_as_ram.lds endif
-ifeq ($(CONFIG_BIG_BOOTBLOCK),y) -ifeq ($(CONFIG_ROMCC),y) -crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc -endif -endif - ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/i386/llshell/llshell.inc endif @@ -196,10 +189,6 @@ ifeq ($(CONFIG_ROMCC),y) ROMCCFLAGS ?= -mcpu=p2 -O2
-$(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c - printf " ROMCC failover.inc\n" - $(obj)/romcc $(ROMCCFLAGS) --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@ - $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/romcc $(OPTION_TABLE_H) $(obj)/build.h printf " ROMCC romstage.inc\n" $(obj)/romcc $(ROMCCFLAGS) -include $(obj)/build.h $(INCLUDES) $< -o $@
Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c Thu Mar 18 17:18:58 2010 (r5257) @@ -25,30 +25,6 @@ { unsigned int cpu_reset = 0;
-#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK -#if CONFIG_USE_FALLBACK_IMAGE == 1 - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } else { - /* This is the primary cpu how should I boot? */ - check_cmos_failed(); - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - ); - fallback_image: -#endif -#endif - real_main(bist);
/* No servicable parts below this line .. */
Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c Thu Mar 18 17:18:58 2010 (r5257) @@ -27,30 +27,6 @@ { unsigned int cpu_reset = 0;
-#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK -#if CONFIG_USE_FALLBACK_IMAGE == 1 - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } else { - /* This is the primary cpu how should I boot? */ - check_cmos_failed(); - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - ); - fallback_image: -#endif -#endif - real_main(bist);
/* No servicable parts below this line .. */
Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c Thu Mar 18 17:18:58 2010 (r5257) @@ -27,30 +27,6 @@ { unsigned int cpu_reset = 0;
-#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK -#if CONFIG_USE_FALLBACK_IMAGE == 1 - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } else { - /* This is the primary cpu how should I boot? */ - check_cmos_failed(); - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - ); - fallback_image: -#endif -#endif - real_main(bist);
/* No servicable parts below this line .. */
Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -100,60 +100,10 @@
#include "cpu/amd/model_fxx/fidvid.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -161,6 +111,14 @@ struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + }
if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/amd/mahogany/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -100,60 +100,10 @@
#include "cpu/amd/model_fxx/fidvid.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb700_lpc_port80(); */ - sb700_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -161,6 +111,15 @@ struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb700_lpc_port80(); */ + sb700_pci_port80(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); }
Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/amd/pistachio/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -94,60 +94,10 @@
#include "cpu/amd/model_fxx/fidvid.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - sb600_lpc_port80(); - /* sb600_pci_port80(); */ - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } - normal_image: - post_code(0x01); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx)); /* inputs */ - - fallback_image: - post_code(0x02); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -157,6 +107,15 @@ (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + sb600_lpc_port80(); + /* sb600_pci_port80(); */ + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); }
Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/arima/hdama/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -95,66 +95,11 @@
#include "cpu/amd/model_fxx/init_cpus.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -169,6 +114,15 @@ struct mem_controller ctrl[8]; unsigned nodes;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -176,68 +176,8 @@ pnp_exit_ext_func_mode(GPIO_DEV); }
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* unsigned last_boot_normal_x = last_boot_normal(); */ - /* FIXME */ - unsigned last_boot_normal_x = 1; - - sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); - console_init(); - enable_rom_decode(); - - print_info("now booting... fallback\r\n"); - - /* Is this a CPU only reset? Or is this a secondary CPU? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) - goto normal_image; - else - goto fallback_image; - } - - /* Nothing special needs to be done to find bus 0. */ - /* Allow the HT devices to be found. */ - enumerate_ht_chain(); - - /* Is this a deliberate reset by the BIOS? */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary CPU, how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } - -normal_image: - /* print_info("JMP normal image\r\n"); */ - - __asm__ __volatile__("jmp __normal_image": - :"a" (bist), "b" (cpu_init_detectedx)); - -fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr[] = { (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, @@ -254,6 +194,21 @@
sio_init(); w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\r\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); enable_rom_decode();
Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/broadcom/blast/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -106,74 +106,10 @@
#include "cpu/amd/model_fxx/init_cpus.c"
- -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - - - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { // RTC already inited - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - bcm5785_enable_rom(); - - bcm5785_enable_lpc(); - - //enable RTC - pc87417_enable_dev(RTC_DEV); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr[] = { RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, @@ -189,6 +125,20 @@ struct mem_controller ctrl[8]; unsigned nodes;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + bcm5785_enable_rom(); + + bcm5785_enable_lpc(); + + //enable RTC + pc87417_enable_dev(RTC_DEV); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/dell/s1850/failover.c ============================================================================== --- trunk/src/mainboard/dell/s1850/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/dell/s1850/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -15,35 +15,5 @@ static unsigned long main(unsigned long bist) { /* skip all this nonsense as we are not doing fallback yet */ - goto fallback_image; - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; }
Modified: trunk/src/mainboard/emulation/qemu-x86/failover.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/emulation/qemu-x86/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -10,20 +10,5 @@
static void main(void) { -#if 0 - /* Is this a cpu reset? */ - if (cpu_init_detected()) { - if (last_boot_normal()) { - asm("jmp __normal_image"); - } else { - asm("jmp __cpu_reset"); - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - asm("jmp __normal_image"); - } -#endif }
Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/ibm/e325/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -93,67 +93,11 @@ #include "cpu/amd/model_fxx/init_cpus.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -179,6 +123,15 @@
int needs_reset;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/ibm/e326/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -92,68 +92,11 @@
#include "cpu/amd/model_fxx/init_cpus.c"
- -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -179,6 +122,15 @@
int needs_reset;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/intel/jarrell/failover.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/intel/jarrell/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -14,34 +14,5 @@
static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; }
Modified: trunk/src/mainboard/intel/xe7501devkit/failover.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/intel/xe7501devkit/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -13,36 +13,5 @@
static unsigned long main(unsigned long bist) { - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else { - - check_cmos_failed(); - - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); -#if 0 - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); -#endif - fallback_image: return bist; }
Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/kontron/kt690/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -101,60 +101,10 @@
#include "cpu/amd/model_fxx/fidvid.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ device_t dev; static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; @@ -163,6 +113,14 @@ struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + }
if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/msi/ms9185/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -153,73 +153,10 @@
#include "cpu/amd/model_fxx/fidvid.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { // RTC already inited - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - bcm5785_enable_rom(); - - bcm5785_enable_lpc(); - - //enable RTC - pc87417_enable_dev(RTC_DEV); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; - -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr[] = { //first node RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, @@ -237,6 +174,20 @@ int needs_reset; unsigned bsp_apicid = 0;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + bcm5785_enable_rom(); + + bcm5785_enable_lpc(); + + //enable RTC + pc87417_enable_dev(RTC_DEV); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); }
Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/msi/ms9282/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -133,8 +133,6 @@ #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
@@ -156,68 +154,12 @@
} -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the mcp55 */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -}
//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1. #define RC0 (2<<8) #define RC1 (1<<8)
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6, @@ -233,6 +175,18 @@ struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); char *p ;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + } + if (bist == 0) { //init_cpus(cpu_init_detectedx); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/newisys/khepri/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -108,71 +108,11 @@ #include "cpu/amd/model_fxx/init_cpus.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the amd8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -188,6 +128,16 @@ struct mem_controller ctrl[8]; unsigned nodes;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the amd8111 */ + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/olpc/btest/failover.c ============================================================================== --- trunk/src/mainboard/olpc/btest/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/olpc/btest/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -9,27 +9,5 @@
static unsigned long main(unsigned long bist) { -#if 0 - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: -#endif return bist; }
Modified: trunk/src/mainboard/olpc/rev_a/failover.c ============================================================================== --- trunk/src/mainboard/olpc/rev_a/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/olpc/rev_a/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -9,27 +9,5 @@
static unsigned long main(unsigned long bist) { -#if 0 - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: -#endif return bist; }
Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -112,8 +112,6 @@ #include "cpu/amd/model_fxx/init_cpus.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
@@ -146,65 +144,8 @@
}
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -220,6 +161,18 @@ struct mem_controller ctrl[8]; unsigned nodes;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/supermicro/x6dai_g/failover.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/supermicro/x6dai_g/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -14,34 +14,5 @@
static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; }
Modified: trunk/src/mainboard/supermicro/x6dhe_g/failover.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/supermicro/x6dhe_g/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -14,34 +14,5 @@
static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; }
Modified: trunk/src/mainboard/supermicro/x6dhe_g2/failover.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/supermicro/x6dhe_g2/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -14,34 +14,5 @@
static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; }
Modified: trunk/src/mainboard/supermicro/x6dhr_ig/failover.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/supermicro/x6dhr_ig/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -14,34 +14,5 @@
static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; }
Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/failover.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -14,34 +14,5 @@
static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; }
Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -103,61 +103,10 @@ #include "tn_post_code.c" #include "speaker.c"
- -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -165,6 +114,15 @@ struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + } + technexion_post_code_init(); technexion_post_code(LED_MESSAGE_START);
Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -100,60 +100,10 @@
#include "cpu/amd/model_fxx/fidvid.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -162,6 +112,15 @@ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); }
Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2735/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -80,53 +80,7 @@
#include "cpu/x86/car/copy_and_run.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - -#include "southbridge/intel/i82801ex/cmos_failover.c" - -void real_main(unsigned long bist); - -void amd64_main(unsigned long bist) -{ - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else { - check_cmos_failed(); - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - ); - cpu_reset: -// post_code(0x24); -#if 0 - //CPU reset will reset memtroller ??? - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - ); -#endif - - fallback_image: -// post_code(0x25); - real_main(bist); -} -void real_main(unsigned long bist) -#else void amd64_main(unsigned long bist) -#endif { static const struct mem_controller memctrl[] = { {
Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2850/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -93,72 +93,11 @@
#include "cpu/amd/model_fxx/init_cpus.c"
- -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the amd8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -173,6 +112,16 @@
int needs_reset;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the amd8111 */ + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2875/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -84,69 +84,11 @@
#include "cpu/amd/model_fxx/init_cpus.c"
- -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx)/* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -172,6 +114,15 @@
int needs_reset;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2880/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -85,68 +85,11 @@
#include "cpu/amd/model_fxx/init_cpus.c"
- -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -172,6 +115,15 @@
int needs_reset;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2881/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -98,72 +98,11 @@
#include "cpu/amd/model_fxx/init_cpus.c"
- -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the amd8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -179,6 +118,16 @@ struct mem_controller ctrl[8]; unsigned nodes;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the amd8111 */ + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2882/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -88,68 +88,11 @@
#include "cpu/amd/model_fxx/init_cpus.c"
- -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -175,6 +118,15 @@
int needs_reset;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2885/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -98,72 +98,11 @@
#include "cpu/amd/model_fxx/init_cpus.c"
- -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the amd8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -179,6 +118,16 @@ struct mem_controller ctrl[8]; unsigned nodes;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the amd8111 */ + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2891/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -77,8 +77,6 @@
#include "cpu/amd/model_fxx/init_cpus.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
@@ -112,68 +110,8 @@
}
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -189,6 +127,18 @@ struct mem_controller ctrl[8]; unsigned nodes;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2892/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -82,8 +82,6 @@
#include "cpu/amd/model_fxx/init_cpus.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
@@ -101,66 +99,8 @@ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); }
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -176,6 +116,18 @@ struct mem_controller ctrl[8]; unsigned nodes;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s4880/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -111,68 +111,11 @@
#include "cpu/amd/model_fxx/init_cpus.c"
- -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -222,6 +165,15 @@
int needs_reset;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s4882/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -119,67 +119,11 @@
#include "cpu/amd/model_fxx/init_cpus.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" ( cpu_init_detectedx ) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, @@ -201,6 +145,15 @@ struct mem_controller ctrl[8]; unsigned nodes;
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); }
Modified: trunk/src/mainboard/via/epia-m/failover.c ============================================================================== --- trunk/src/mainboard/via/epia-m/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/via/epia-m/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -9,27 +9,5 @@
static unsigned long main(unsigned long bist) { -#if 0 - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: -#endif return bist; }
Modified: trunk/src/mainboard/via/epia-n/failover.c ============================================================================== --- trunk/src/mainboard/via/epia-n/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/via/epia-n/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -9,27 +9,5 @@
static unsigned long main(unsigned long bist) { -#if 0 - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: -#endif return bist; }