Thanks Wim.
I will give a try and pass a 512 byte hex block corresponding to the SPD data and if it works, I can play with the hex values to find out the right configuration.
BTW, any idea which field can impact the ddrfreq which was reported as error in the initial logs?
Regards, Naveen
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________________________________ From: Wim Vervoorn wvervoorn@eltan.com Sent: Tuesday, October 29, 2019 3:07:44 PM To: Nico Huber nico.h@gmx.de; Naveen Chaudhary naveenchaudhary2010@hotmail.com; David Hendricks david.hendricks@gmail.com Cc: coreboot@coreboot.org coreboot@coreboot.org Subject: RE: [coreboot] Re: Coreboot FSP fails to initialize RAM - "Configuration not in POR table"
Hello Naveen,
You should use the "MemDownCh0Dimm0SpdPtr" to point to a buffer containing the SPD data and set MemDownEnable" to 1.
Best Regards, Wim Vervoorn
-----Original Message----- From: Nico Huber [mailto:nico.h@gmx.de] Sent: Sunday, October 27, 2019 11:33 AM To: Naveen Chaudhary naveenchaudhary2010@hotmail.com; David Hendricks david.hendricks@gmail.com Cc: coreboot@coreboot.org Subject: [coreboot] Re: Coreboot FSP fails to initialize RAM - "Configuration not in POR table"
Hello Naveen,
On 27.10.19 05:02, Naveen Chaudhary wrote:
Does this mean that there is a way in FSP to define custom settings(configs) for DIMMs? In the FSP integration guide for BroadwellDE (https://github.com/IntelFsp/FSP/tree/master/BroadwellDEFspBinPkg/Docs) I don't see any relevant data member where we could define pointer to custom SPD settings or pass individual DIMMs configurations.
there is the memory-down option. It seems undocumented if that does more than switching from on-DIMM SPDs to SPD files. Maybe it's worth a try. If that doesn't work out, you can always overwrite the SPDs on your DIMM's EEPROMs. Always keep a backup, though.
Hope that helps, Nico _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org