15 Jan
2009
15 Jan
'09
10:03 p.m.
Hi,
I have two DDR2 DIMMS with 2 GB each, but coreboot refuses to use them in a dualchannel setup. Instead, one DIMM is ignored.
I have attached the result from decode-dimms.
Regards, Carl-Daniel
--
http://www.hailfinger.org/
Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/0-0050
Guessing DIMM is in bank 1
---=== SPD EEPROM Information ===---
EEPROM Checksum of bytes 0-62 OK (0x18)
# of bytes written to SDRAM EEPROM 128
Total number of bytes in EEPROM 256
Fundamental Memory type DDR2 SDRAM
SPD Revision 1.2
---=== Memory Characteristics ===---
Maximum module speed 800MHz (PC2-6400)
Size 2048 MB
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64
Ranks 2
SDRAM Device Width 8 bits
Module Height 30.0 mm
Module Type UDIMM (133.25 mm)
DRAM Package Planar
Voltage Interface Level SSTL 1.8V
Refresh Rate Reduced (7.8 us) - Self Refresh
Supported Burst Lengths 4, 8
tCL-tRCD-tRP-tRAS 5-5-5-18
Supported CAS Latencies (tCL) 5T, 4T
Minimum Cycle Time at CAS 5 (tCK min) 2.50 ns
Maximum Access Time at CAS 5 (tAC) 0.40 ns
Minimum Cycle Time at CAS 4 3.75 ns
Maximum Access Time at CAS 4 0.50 ns
Maximum Cycle Time (tCK max) 8.00 ns
---=== Timing Parameters ===---
Address/Command Setup Time Before Clock (tIS) 0.17 ns
Address/Command Hold Time After Clock (tIH) 0.25 ns
Data Input Setup Time Before Strobe (tDS) 0.05 ns
Data Input Hold Time After Strobe (tDH) 0.12 ns
Minimum Row Precharge Delay (tRP) 12.50 ns
Minimum Row Active to Row Active Delay (tRRD) 7.50 ns
Minimum RAS# to CAS# Delay (tRCD) 12.50 ns
Minimum RAS# Pulse Width (tRAS) 45.00 ns
Write Recovery Time (tWR) 15.00 ns
Minimum Write to Read CMD Delay (tWTR) 7.50 ns
Minimum Read to Pre-charge CMD Delay (tRTP) 7.50 ns
Minimum Active to Auto-refresh Delay (tRC) 60.00 ns
Minimum Recovery Delay (tRFC) 127.50 ns
Maximum DQS to DQ Skew (tDQSQ) 0.20 ns
Maximum Read Data Hold Skew (tQHS) 0.30 ns
---=== Manufacturing Information ===---
Manufacturer Mushkin
Manufacturing Location Code 0x01
Part Number 991558 (996558)
Manufacturing Date 2008-W02
Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/0-0051
Guessing DIMM is in bank 2
---=== SPD EEPROM Information ===---
EEPROM Checksum of bytes 0-62 OK (0x4A)
# of bytes written to SDRAM EEPROM 128
Total number of bytes in EEPROM 256
Fundamental Memory type DDR2 SDRAM
SPD Revision 1.2
---=== Memory Characteristics ===---
Maximum module speed 800MHz (PC2-6400)
Size 2048 MB
Banks x Rows x Columns x Bits 8 x 14 x 10 x 64
Ranks 2
SDRAM Device Width 8 bits
Module Height 30.0 mm
Module Type UDIMM (133.25 mm)
DRAM Package Planar
Voltage Interface Level SSTL 1.8V
Refresh Rate Reduced (7.8 us) - Self Refresh
Supported Burst Lengths 4, 8
tCL-tRCD-tRP-tRAS 6-5-5-18
Supported CAS Latencies (tCL) 6T, 5T, 4T
Minimum Cycle Time at CAS 6 (tCK min) 2.50 ns
Maximum Access Time at CAS 6 (tAC) 0.40 ns
Minimum Cycle Time at CAS 5 2.50 ns
Maximum Access Time at CAS 5 0.40 ns
Minimum Cycle Time at CAS 4 3.75 ns
Maximum Access Time at CAS 4 0.50 ns
Maximum Cycle Time (tCK max) 8.00 ns
---=== Timing Parameters ===---
Address/Command Setup Time Before Clock (tIS) 0.17 ns
Address/Command Hold Time After Clock (tIH) 0.25 ns
Data Input Setup Time Before Strobe (tDS) 0.05 ns
Data Input Hold Time After Strobe (tDH) 0.12 ns
Minimum Row Precharge Delay (tRP) 12.50 ns
Minimum Row Active to Row Active Delay (tRRD) 7.50 ns
Minimum RAS# to CAS# Delay (tRCD) 12.50 ns
Minimum RAS# Pulse Width (tRAS) 45.00 ns
Write Recovery Time (tWR) 15.00 ns
Minimum Write to Read CMD Delay (tWTR) 7.50 ns
Minimum Read to Pre-charge CMD Delay (tRTP) 7.50 ns
Minimum Active to Auto-refresh Delay (tRC) 57.00 ns
Minimum Recovery Delay (tRFC) 127.50 ns
Maximum DQS to DQ Skew (tDQSQ) 0.20 ns
Maximum Read Data Hold Skew (tQHS) 0.30 ns
---=== Manufacturing Information ===---
Manufacturer AENEON
Manufacturing Location Code E
Part Number AET860UD00-25DC08X
Revision Code 0x0143
Manufacturing Date 2008-W13
Assembly Serial Number 0x1503005C