Hi Balaji,
I see that SPI BIOS_CTRL.LE bit is set. It can be set by either Coreboot or FSP. I guess it might be getting set by FSP. Can you add printk in file "src/soc/intel/denverton_ns/chip.c" at the line 46 before & after fsp_silicon_init to print bios control reg. This will help in understanding whether fsp is doing it or not.
If SOC_INTEL_COMMON_PCH_LOCKDOWN config is enabled in your build then src/soc/intel/common/block/fast_spi/fast_spi.c +102 here it might be getting locked.
Also you can enable debug log in smi handler & print bios control reg select this in menuconfig CONFIG_DEBUG_SMI
If possible, provide a log with above debug prints to understand where the lock enable bit is getting set.
Regards, Naresh Solanki
On Tue, Nov 10, 2020 at 12:40 PM David Hendricks david.hendricks@gmail.com wrote:
Hi Balaji,
On Tue, Nov 3, 2020 at 10:03 PM Balaji Sivakumar shivbalaji1985@gmail.com wrote:
Hi David,
Have verified and confirmed that coreboot process as well, it is disabling the BIOS write protect and Enable Prefetching and Caching as part of fast_spi_init().
Were you able to figure this one out? The snippet you showed is from fast_spi_init() which should get called once early on. It is possible that something later on calls fast_spi_enable_wp(), perhaps smihandler_soc_check_illegal_access(). _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org