No, I didn't mean intel chipsets (did I say chipsets? If so, I'm sorry), I meant the CPUs. I've been through the docs enough to check that the current init for P3s will work for all current Intel CPUs, with the exception of having the microcode updates for the newer CPUs. All my patch does is better organize the current CPUs, add the CPU IDs and appropriate socket folders for the newer ones, and add the microcode updates for every PII and newer CPU, including Xeons. Unfortunately, those updates are too large to fit in the rom for some socket types/mainboards currently in the tree, so something needs to be done to make them fit. You'll have to take care of the rest of the chipset yourself ;)
Good luck! -Corey
On Sun, Jun 29, 2008 at 2:59 AM, Patrick Georgi patrick@georgi-clan.de wrote:
Star Liu schrieb:
I'm a little confused. We had a discussion in the coreboot IRC room yesterday. We thought that intel do not provide public information on how to initiate and test their chipset, so we are not able to provide support to those intel chipset in coreboot.
They might provide information under NDAs (non-disclosure agreements). Other vendors also do that, but that's okay if someone is willing to sign an NDA and if the NDA allows distribution of the resulting code under the terms of the GPL, maybe after getting clearance from the vendor.
The issue seems to be that intel is less willing to do that than others, and if they are, they seem to move rather slowly.
Regards, Patrick Georgi
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