On Wed, Jan 14, 2009 at 03:04:09AM +0100, Luc Verhaegen wrote:
The first one i looked at was the aforementioned and this here is what is needed for the flash enable of that board.
{ uint8_t tmp;
pci_write_byte(dev, 0x92, 0);
tmp = pci_read_byte(dev, 0x6D); tmp |= 0x01; pci_write_byte(dev, 0x6D, tmp); }
While it seems that the second operation seems to match both ck804 and mcp55 chip enables, this is not true. The device used is 0:01.0 (ISA bridge) and not 0:01.1 (SMB controller).
I googled, but could not find a report to the coreboot (or linuxbios) list of this board being tested. Does anyone remember who reported this as broken?
Luc Verhaegen.
Anyone have any contact information for who reported this to begin with? Because that is the only thing that's standing in the way of adding chipset/board support for this hw.
I fear that this was an irc discussion somewhere, and here the lack of logging is seriously hampering progress.
Luc Verhaegen.