Author: hailfinger Date: 2008-02-18 02:43:50 +0100 (Mon, 18 Feb 2008) New Revision: 607
Modified: coreboot-v3/mainboard/adl/msm800sev/dts coreboot-v3/mainboard/amd/norwich/dts coreboot-v3/mainboard/artecgroup/dbe61/dts coreboot-v3/mainboard/pcengines/alix1c/dts Log: Update mainboard dts files to new style. Untested, but I tried to keep the new settings as close as possible to the old settings. All GeodeLX-based boards now include the geodelx/domain, geodelx/apic and geodelx/pci dts files.
Remove "enabled" keyword from the alix.1c main dts. (That's the only possibly critical change because it affects a working target. Tests on hardware appreciated. Should be harmless, though.)
Compile tested only for msm800sev, norwich and dbe61, and the situation is better than without the patch.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Tested and boots a working linux on alix1c.
Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/mainboard/adl/msm800sev/dts =================================================================== --- coreboot-v3/mainboard/adl/msm800sev/dts 2008-02-18 00:48:25 UTC (rev 606) +++ coreboot-v3/mainboard/adl/msm800sev/dts 2008-02-18 01:43:50 UTC (rev 607) @@ -23,22 +23,19 @@ /{ mainboard-vendor = "Advanced Digital Logic"; mainboard-name = "MSM800SEV"; - cpus { - enabled; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); }; - domain0 { - enabled; - pcidomain = "0"; - device0,0 { - enabled; - pcipath = "1,0"; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); }; - southbridge { + pci@1,1 { /config/("southbridge/amd/cs5536/dts"); - pcipath = "1,1"; - enabled; }; - superio { + ioport@46 { /config/("superio/winbond/w83627hf/dts"); com1enable = "1"; };
Modified: coreboot-v3/mainboard/amd/norwich/dts =================================================================== --- coreboot-v3/mainboard/amd/norwich/dts 2008-02-18 00:48:25 UTC (rev 606) +++ coreboot-v3/mainboard/amd/norwich/dts 2008-02-18 01:43:50 UTC (rev 607) @@ -19,23 +19,19 @@ */
/{ - enabled; mainboard-vendor = "AMD"; mainboard-name = "Norwich"; - cpus { - enabled; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); }; - domain0 { - enabled; - pcidomain = "0"; - device0,0 { - enabled; - pcipath = "1,0"; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); }; - southbridge { + pci@1,1 { /config/("southbridge/amd/cs5536/dts"); - pcipath = "1,1"; - enabled; }; }; };
Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-02-18 00:48:25 UTC (rev 606) +++ coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-02-18 01:43:50 UTC (rev 607) @@ -75,21 +75,17 @@ /{ mainboard-vendor = "Artec Group"; mainboard-name = "DBE61"; - enabled; - cpus { - enabled; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); }; - domain0 { - enabled; - pcidomain = "0"; - device0,0 { - enabled; - pcipath = "1,0"; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); }; - southbridge { + pci@1,1 { /config/("southbridge/amd/cs5536/dts"); - pcipath = "1,1"; - enabled; }; }; };
Modified: coreboot-v3/mainboard/pcengines/alix1c/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/dts 2008-02-18 00:48:25 UTC (rev 606) +++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-02-18 01:43:50 UTC (rev 607) @@ -19,7 +19,6 @@ */
/{ - enabled; mainboard-vendor = "PC Engines"; mainboard-name = "ALIX1.C"; cpus { };