Hi Eero,
the main difference between v1.0 and v2.0 is that v2.0 has 2 type A USB3 ports and it also has more Type A USB2 ports compared to v1.0 due to having an internal USB 2 hub chip. IIRC the v2.0 has two USB type A ports on the side with the 4 Ethernet connectors and the two display connectors, and 4 USB type A ports on the other side. Don't remember the exact configuration on the v1.0, but i think it's missing the 4 USB ports on the non-Ethernet side. If the device has an RJ45 console port, it's a different mainboard.
I generated the GPIO config from the system running with the vendor firmware (IIRC some tool I used for that had some bug) and figured out the PCIe HSIO lane mappings via the PCI bridge device and function of the corresponding bridge, clock outputs and clock requests by disabling some clock outputs in the vendor firmware and see which devices don't show up and the USB port lane mappings via lsusb and plugging in some USB device in different ports. The PCIe config matched between v1.0 and v2.0 minus the bug in the v1.0 code which is now fixed in upstream.
Regards, Felix
On 09/02/2025 19:39, Eero Volotinen wrote:
How to identify if device is v1 or v2?
Eero
su 9.2.2025 klo 20.31 Felix Held (felix-coreboot@felixheld.de mailto:felix-coreboot@felixheld.de) kirjoitti:
Hi, haven't pushed the changes to add the v2.0 as variant of the v1.0 yet and probably won't get around to do that in the next few months. Only spent one evening on getting coreboot to work on the v2.0 device and mainly figured out how things are connected and found some bugs in the v1.0 code while doing that. Those v1.0 fixes are in upstream, but haven't been validated on hardware due to the original author of that port being unresponsive. The main thing that I haven't figured out on the v2.0 is how to make the Type A USB3 ports working, since the super speed lanes of those aren't connected to the PCH's HSIO lines, but to the TCSS ports on the CPU; by the Intel guide that's not a supported configuration. This works under the vendor firmware and I don't see any reason why it shouldn't, but I haven't figured out how to make that work on coreboot+FSP. Regards, Felix On 09/02/2025 19:03, Matt DeVillier wrote: > There is currently support for the CWWK CW-ADL-4L v1.0, and support for > v2.0 is under review, though I'm not sure if either is 100% working > > Adding Felix Held to the chain, as I think he's been working on one/both > versions > > cheers, > Matt > > On Sun, Feb 9, 2025 at 7:35 AM Eero Volotinen <eero.volotinen@iki.fi <mailto:eero.volotinen@iki.fi> > <mailto:eero.volotinen@iki.fi <mailto:eero.volotinen@iki.fi>>> wrote: > > Hi, > > Is there any cheap firewall box at aliexpress that can support coreboot? > > Eero > _______________________________________________ > coreboot mailing list -- coreboot@coreboot.org <mailto:coreboot@coreboot.org> > <mailto:coreboot@coreboot.org <mailto:coreboot@coreboot.org>> > To unsubscribe send an email to coreboot-leave@coreboot.org <mailto:coreboot-leave@coreboot.org> > <mailto:coreboot-leave@coreboot.org <mailto:coreboot- leave@coreboot.org>> >