I use coreboot for ApolloLake CPU (Atom). We have SuperIO WB83627-DHG chip on carrier board. LPC enabled, POST codes work normal. But I can't get access to SIO under Linux (via port 0x2e). Superiotool can't find chip. Also, I have CPLD on LPCB - I use it to view LPC transactions - so, then I try to out byte to 0x2e - transaction on LPC is none. But, I enable UART0 on SIO (via devicetree.cb) - and it works fine. Whats wrong?
*Devtree (part):* device pci 1f.0 on # - LPC chip superio/winbond/w83627dhg device pnp 2e.0 off end # Floppy device pnp 2e.1 off end # Parallel Port device pnp 2e.2 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 off # COM2 end device pnp 2e.5 off # Keyboard end device pnp 2e.6 off # SPI end device pnp 2e.307 off # GPIO 1 end device pnp 2e.8 off # WDTO#, PLED end device pnp 2e.009 off # GPIO2 end device pnp 2e.109 off # GPIO3 end device pnp 2e.209 off # GPIO4 end device pnp 2e.309 off # GPIO5 end device pnp 2e.a off # ACPI end device pnp 2e.b off # HWM end device pnp 2e.c off # PECI, SST end end # w83627dhg
*PNP020C (in /sys/bus/pnp/devices/00:01) resources:*
state = active io 0x2e-0x2f io 0x4e-0x4f io 0x61-0x61 io 0x63-0x63 io 0x65-0x65 io 0x67-0x67 io 0x80-0x80 io 0x92-0x92 io 0xb2-0xb3 io 0x400-0x4fe
*dsdt.asl from coreboot:*
#include <acpi/acpi.h> DefinitionBlock( "dsdt.aml", "DSDT", 0x02, // DSDT revision: ACPI v2.0 and up OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { /* global NVS and variables */ #include <soc/intel/apollolake/acpi/globalnvs.asl>
/* CPU */ #include <cpu/intel/common/acpi/cpu.asl>
Scope (_SB) { Device (PCI0) { #include <soc/intel/apollolake/acpi/northbridge.asl> #include <soc/intel/apollolake/acpi/southbridge.asl> #include <soc/intel/apollolake/acpi/pch_hda.asl> } }
#include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (_SB.PCI0.LPCB) { #include <acpi/ec.asl> /* ec is empty */ #include <acpi/superio.asl> }
}