Siyuan Wang (wangsiyuanbuaa@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1593
-gerrit
commit 26a63191f0d914cedeee93d37b143826e282f91e Author: Siyuan Wang wangsiyuanbuaa@gmail.com Date: Fri Oct 19 21:47:00 2012 +0800
cimx wrapper: move to romstage
We move 5 cimx wrappers to romstage: Pcie_Early_Init, Pcie_Late_Init Early_Post_Init, Mid_Post_Init and Late_Post_Init. The reasons we do these changes are: 1) The pcie bridge with devices shoud be on and without devices should be off before device enumerate. 2) Now, the code do pcie training in device enable. So the pcie bridge is scanned whether there is a device or not. This could lead to some errors. For example: coreboot scans device tree twice and gets two different VGA devices, so the VGA bios could not be loaded correctly.
We leave an empty rd890_enable for further use.
Change-Id: I4bb6b54823cd08eae94b224130b46cc20b3ec43f Signed-off-by: Siyuan Wang SiYuan.Wang@amd.com Signed-off-by: Siyuan Wang wangsiyuanbuaa@gmail.com --- src/northbridge/amd/cimx/rd890/early.c | 25 ++++++ src/northbridge/amd/cimx/rd890/late.c | 146 +------------------------------ src/northbridge/amd/cimx/rd890/nb_cimx.h | 12 +-- 3 files changed, 33 insertions(+), 150 deletions(-)
diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c index 8008223..1286954 100644 --- a/src/northbridge/amd/cimx/rd890/early.c +++ b/src/northbridge/amd/cimx/rd890/early.c @@ -111,3 +111,28 @@ void nb_S3_Init(void) { //TODO } + +void nb_Pcie_Early_Init(AMD_NB_CONFIG_BLOCK *pConfig) +{ + LibSystemApiCall(AmdPcieEarlyInit, pConfig); +} + +void nb_Pcie_Late_Init(AMD_NB_CONFIG_BLOCK *pConfig) +{ + LibSystemApiCall(AmdPcieLateInit, pConfig); +} + +void nb_Early_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig) +{ + LibSystemApiCall(AmdEarlyPostInit, pConfig); +} + +void nb_Mid_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig) +{ + LibSystemApiCall(AmdMidPostInit, pConfig); +} + +void nb_Late_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig) +{ + LibSystemApiCall(AmdLatePostInit, pConfig); +} diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index 33da2b4..53aabe5 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -27,151 +27,9 @@ #include "nb_cimx.h" #include "rd890_cfg.h"
- -/** - * Global RD890 CIMX Configuration structure - */ -static NB_CONFIG nb_cfg[MAX_NB_COUNT]; -static HT_CONFIG ht_cfg[MAX_NB_COUNT]; -static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; -static AMD_NB_CONFIG_BLOCK gConfig; - - -/** - * Reset PCIE Cores, Training the Ports selected by port_enable of devicetree - * After this call EP are fully operational on particular NB - */ -void nb_Pcie_Early_Init(void) -{ - LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig); -} - -void nb_Pcie_Late_Init(void) -{ - LibSystemApiCall(AmdPcieLateInit, &gConfig); -} - -void nb_Early_Post_Init(void) -{ - LibSystemApiCall(AmdEarlyPostInit, &gConfig); -} - -void nb_Mid_Post_Init(void) -{ - LibSystemApiCall(AmdMidPostInit, &gConfig); -} - -void nb_Late_Post_Init(void) -{ - LibSystemApiCall(AmdLatePostInit, &gConfig); -} - static void rd890_enable(device_t dev) { - u32 address = 0; - u32 mask; - u32 val; - u32 devfn; - u32 port; - AMD_NB_CONFIG *NbConfigPtr = NULL; - - u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */ - address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); - NbConfigPtr = &(gConfig.Northbridges[nb_index]); - - devfn = dev->path.pci.devfn; - port = devfn >> 3; - printk(BIOS_INFO, "rd890_enable "); - printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n", - 0, (devfn >> 3), (devfn & 0x07), dev->enabled); - if (port != 0) { - if (dev->enabled) { - NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = OFF; - } else { - NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = ON; - } - } - - switch (port) { - case 0x0: /* Root Complex, and ClkConfig */ - - if ((devfn & 0x07) == 1) { /* skip dev-0 fun-1 */ - break; - } - - /* CIMX configuration defualt initialize */ - rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); - if (gConfig.StandardHeader.CalloutPtr != NULL) { - /* NOTE: not use LibNbCallBack */ - gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); - } - /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree - * After this call EP are fully operational on particular NB - */ - nb_Pcie_Early_Init(); - break; - - case 0x2: /* Gpp1 Port0 */ - case 0x3: /* Gpp1 Port1 */ - mask = ~(1 << port); - val = (dev->enabled ? 0 : 1) << port; - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0x4: /* Gpp3a Port0 */ - case 0x5: /* Gpp3a Port1 */ - case 0x6: /* Gpp3a Port2 */ - case 0x7: /* Gpp3a Port3 */ - mask = ~(1 << port); - val = (dev->enabled ? 0 : 1) << port; - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0x8: /* SB ALink */ - mask = ~(1 << 6); - val = (dev->enabled ? 1 : 0) << 6; - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0x9: /* Gpp3a Port4 */ - case 0xa: /* Gpp3a Port5 */ - mask = ~(1 << (7 + port)); - val = (dev->enabled ? 0 : 1) << (7 + port); - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0xb: /* Gpp2 Port0 */ - case 0xc: /* Gpp2 Port1 */ - mask = ~(1 << (7 + port)); - val = (dev->enabled ? 0 : 1) << (7 + port); - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0xd: /* Gpp3b */ - mask = ~(1 << (7 + port)); - val = (dev->enabled ? 0 : 1) << (7 + port); - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - - /* Init NB at Early Post */ - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Early_Post_Init();// - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Mid_Post_Init(); - nb_Pcie_Late_Init(); - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Late_Post_Init(); - break; - - default: - printk(BIOS_INFO, "Buggy Device Tree\n"); - break; - } + //TODO }
struct chip_operations northbridge_amd_cimx_rd890_ops = { @@ -179,7 +37,6 @@ struct chip_operations northbridge_amd_cimx_rd890_ops = { .enable_dev = rd890_enable, };
- static void ioapic_init(struct device *dev) { u32 ioapic_base; @@ -196,7 +53,6 @@ static void rd890_read_resource(struct device *dev) /* rpr6.2.(1). Write the Base Address Register (BAR) */ pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ - compact_resources(dev); }
diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h index a6f77db..65dcbc3 100644 --- a/src/northbridge/amd/cimx/rd890/nb_cimx.h +++ b/src/northbridge/amd/cimx/rd890/nb_cimx.h @@ -20,6 +20,8 @@ #ifndef _NB_CIMX_H_ #define _NB_CIMX_H_
+#include "NbPlatform.h" + /** * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b * @@ -34,11 +36,11 @@ void sr56x0_rd890_disable_pcie_bridge(void); void nb_Poweron_Init(void); void nb_Ht_Init(void); void nb_S3_Init(void); -void nb_Early_Post_Init(void); -void nb_Mid_Post_Init(void); -void nb_Late_Post_Init(void); -void nb_Pcie_Early_Init(void); -void nb_Pcie_Late_Init(void); +void nb_Pcie_Early_Init(AMD_NB_CONFIG_BLOCK *pConfig); +void nb_Pcie_Late_Init(AMD_NB_CONFIG_BLOCK *pConfig); +void nb_Early_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig); +void nb_Mid_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig); +void nb_Late_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig);
#endif//_RD890_EARLY_H_