On Thu, Sep 7, 2017 at 11:03 AM Timothy Pearson < tpearson@raptorengineering.com> wrote:
could anyone shed some light on these decision making processes? An open ISA and core design does not guarantee open silicon, and in fact one could argue that it will mean any performance improvements end up highly locked under NDA and similar to avoid competitors coming online and ruining tens of millions of dollars of investment for even one SoC improvement.
Exactly. The open ISA can go both ways: pushing toward "value adds" that lock up a platform, instead of going the way we might hope, so vendors have competitive advantage. Look at page 47 of "Volume II: RISC-V Privileged Architectures V1.10" -- it basically allows a vendor to recreate SMM as it exists today, creating regions of memory irrevocably hidden from kernel. And there are certain things you can't access on riscv without an M-mode trap, which means that you can't escape the need for code in M mode.
RISCV vendors can create SMM. We need to encourage creation of a world in which they do not. But just claiming that "riscv is open so there won't be anything proprietary" is being a bit unrealistic in my view.
So what about Power? The problem I keep hearing is that power competes in the server space with x86, and not well enough. It's one of too slow, too power hungry, or too expensive right now to compete well. I am hoping that Raptor is going to show us power done right :-)
ron