Votier, Sean (DS-1) wrote:
these chipsets is there some basic legacy I/O mapping for parallel, serial and other real mode devices by default on power up?
Not sure, but I believe not - you usually need to configure that legacy hardware stuff.
Maybe some GPIO on the FWH is reachable already very early; assuming that the addresses needed to read it are decoded to the FWH..
I'm hoping that something similar happens to the way that the Firmware Hub is made to look like a BIOS rom on power up.
The FWH is a flash chip on a LPC bus. The chipset needs to come up in a way that CPU fetch from the reset vector is decoded to the flash.
I need to read one GPIO pin very early in the bios initialisation and hope I can just look at a bit at I/O address 378.
My guess is that another solution would be better.
//Peter