Re: [coreboot] Remaining ROMCC targets

[Joseph Smith]

> http://download.intel.com/design/PentiumIII/datashts/27367305.pdf
>
> It just says:
> • On-die primary (L1) instruction and data caches
>   — 4-way set associative, 32-byte line size, 1 line per sector
>   — 16-Kbyte instruction cache and 16-Kbyte write-back data cache
>   — Cacheable range controlled by processor programmable registers
> • On-die second level (L2) cache
>   — 8-way set associative, 32-byte line size, 1 line per sector
>   — Operates at full core speed
>   — 512-Kbyte ECC protected cache data array

Oh does that mean the L1 cache is 16K? That seems so small...