* Ward Vandewege ward@gnu.org [060511 23:50]:
0000:01:04.3 Bridge: Advanced Micro Devices [AMD] AMD-8111 ACPI (rev 05) ... -40: 80 f1 00 04 00 00 00 00 20 14 50 00 00 00 00 00 +40: 80 f1 00 07 00 00 00 00 20 14 50 00 00 00 00 00
Try the attached patch
That didn't help. 0x43 was still set to 04, and I could not set the fan speed. There was a bracket missing from the patch, btw.
Looking at the datasheet of the 8111 this was a blind shot in the wrong direction.
The bits 0:2 in this register are:
PPSTATE. Previous power state. Read-only. This field holds the most previous power state from which the system came into the FON state. This field resides on the VDD_COREX plane. Here are the possible states:
PPSTATE Power state 0h Reserved 1h POS power on suspend 2h C2 3h C3 4h MOFF mechanical off 5h STR suspend to RAM 6h STD suspend to disk 7h SOFF soft off
So LinuxBIOS reports mechanical off while factory bios reports soft off. Interesting.
But I found some stuff that is worth following. Fans are controlled by the IO mapped power management registers (PMxx) of the 8111. They are called System Management I/O Mapped Registers in the specs on pages 218 et sqq.
The base of the PMxx registers can be read from DevB:3x58 (32bit) bits 15:8. (ie. pmbase=pci_read_dword(acpi_dev, 0x58) & 0xff00;) See the aruma acpi code for more information. Iirc PMbase is 0xDD00 per default. So PM12 would require inb/outb to 0xdd12.
Also, there's GPIOs connected with FAN control: (pg 244 et sqq) GPIO9 PMC9 FANCON1 08h (FANCON1 output) 1Xb N/A GPIO10 PMCA FANRPM 08h (FANRPM input) 1Xb direct
And on the SMBus you have the following registers: Fan Control Register PMF8 (Sounds like this belongs to the PMxx registers)
Ok, now we need to glue this all together so that it works.
Stefan