I looked for my CL from years back in which I showed a way to 64-bit amd64 ramstage, but I don't see it any more.
But it was easy.
On Tue, Feb 26, 2019 at 2:11 PM Rudolf Marek r.marek@assembler.cz wrote:
Hi,
Dne 26. 02. 19 v 22:58 Nico Huber napsal(a):
On 26.02.19 20:16, ron minnich wrote:
On Tue, Feb 26, 2019 at 6:41 AM Patrick Rudolph patrick.rudolph@9elements.com wrote:
Hi coreboot folks, in order to support TEE like Intel TXT it is necessary to be able to clear all DRAM at boot on request.
As all of the x86 coreboot code is x86_32, it is necessary to make use of PAE to clear memory.
Why PAE, you can you can use 64-bit paging data structures while still running in 32-bits! You simply don't leave compatibility mode and thats all.
- setup 64bit paging structures, set CR3
- set EFER.LME
- enable paging in CR0.PG
- you are done, because now you run in 32-bits but paging structures are 64-bit...
I would much rather we consider getting into the current century and having coreboot be able to run x86_64 :-)> can we do that?
Would be a lot easier if coreboot were open source on x86. But it's still doable, even in the presence of 32-bit blobs.
Though, as it seems, we allow blobs to call into coreboot code now. This means we wouldn't only have to wrap calls into a 32-bit blob, we'd also have to wrap everything that may be called by the blob.
Yes, I can only add that you can jump from/to 64-bit mode using JMP/CALL FAR or equivalent. It is just a matter of changing the CS selector to the desired one. With that, you can have some wrapper to call some routine from 64-bit to 32-bit and vice versa. The only pain is LP64, because "long" is 64-bit...
Thanks, Rudolf