Re: [coreboot] patch: add initram for dbe62

[Marc Jones]

ron minnich wrote:
> This is a first file for the dbe62. I am adding this so others can see
> where to get the data sheet and maybe
> help me get the right values in. :-)
>
> thanks
>
> ron

...
> +/* The part is a Micron MT46V16M16 P 5B
> 4 M x 16 x 5 Banks, 200 Mhz, Plastic package, TSOP, DDR400B, 5 ns CL3
> Commercial rating.
> @ 200 ns, data-out window, 1.6; access, +- 70 ns; dqs-dq skew: .4ns
> http://www.micron.com/products/partdetail?part=MT46V16M16P-5B
> */
>
> +/* SPD array */
> +static const u8 spdbytes[] = {
> [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
> [SPD_BANK_DENSITY] = 0x40,
> [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
> [SPD_MEMORY_TYPE] = 7,
> [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
> [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
> [SPD_NUM_BANKS_PER_SDRAM] = 4,
> [SPD_PRIMARY_SDRAM_WIDTH] = 8,
> [SPD_NUM_DIMM_BANKS] = 1,
> [SPD_NUM_COLUMNS] = 0xa,
> [SPD_NUM_ROWS] = 3,
> [SPD_REFRESH] = 0x3a,
> [SPD_SDRAM_CYCLE_TIME_2ND] = 60,
> [SPD_SDRAM_CYCLE_TIME_3RD] = 75,
> [SPD_tRAS] = 40,
> [SPD_tRCD] = 15,
> [SPD_tRFC] = 70,
> [SPD_tRP] = 15,
> [SPD_tRRD] = 10,
>
> +};
>
> +u8 spd_read_byte(u16 device, u8 address)
> +{
> printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device);
> if (device != (0x50 << 1)) {
> printk(BIOS_DEBUG, " returns 0xff\n");
> return 0xff;
> }
> printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbytes[address]);
> return spdbytes[address];
>
> +}

I see that this is done the same as the alix1c but I prefer the way that 
is done in v2 dbe61.  There are a couple problems with doing it this 
way. This way makes the array as large as the last item. It also doesn't 
check the address against the array size. Last is that unimplemented 
bytes should return FF rather than 0 like a real SPD for error checking 
on the callers side. I admit that all this is low risk since we know 
what values the memory init code uses.

Marc