Stefan Reinauer stepan@suse.de writes:
- ron minnich rminnich@lanl.gov [030624 17:23]:
On 24 Jun 2003, Eric W. Biederman wrote:
I am seeing some odd problems with SST LPC flash chips and any other data point would be interesting... The chips look like they are dropping commands for no good reason.
I heard a similar report recently but the chip was an 82802ab, and the mobo was a supermicro x5 series ... seems like timing problems are "going around"
I have seen one or two problems on the x5. But it is quite rare, I'd say a 1 in 100 or so. With the SST I am seeing problems on every chip of the appropriate model every time I flash. Though with 64bit kernels I see fewer problems.
With devbios you _have_ to disable the nmi watchdog, otherwise it will just kick the dd command out of a write or erase cycle. I hope mtd is written cleaner, but i dont know.
Yes mtd is. The code calls schedule has smp locks etc. I'm not certain another data point will do me any good. But I can hope. When code is stable and you start putting it to more use you see a whole new set of problems, because it is being used more. And I am at that stage with the MTD drivers.
I really appreciate the good factoring of the code. So far there are only 3 real drivers for NOR flash. One for the Intel command set, one for the AMD command set, and one for some weird command set. Then you have them map drivers which know how to find the flash devices. And then there is jedec_probe which knows how to map the device id's to the command set, and chip size. Or cfi_probe if you are so lucky on having and a nice flash chip.
Eric