Re: [coreboot] DL145G3

[FENG Yu Ning]

I wrote:
> Looks like the boot block is write protected (by the controller).

SST49LF080A has a #TBL pin deciding whether writes to the top boot
block is protected.

If that is the cause of the failure and should you have no choice
other than flashrom at the moment, I can see two workarounds.

* if someone has access to the BCM5875(HT1000) datasheet, (s)he may
    check whether there are registers that control the output to the
    #TBL pin, then improves flashrom. Or,

* You can insulate the #TBL pin of the flash chip from the
    corresponding socket contact, and connect #TBL to Vdd. According
    to the datasheet of SST49LF080A, providing Vih(=Vdd) to #TBL
    disables write protection on the boot block.

yu ning