Hi i have a question about this L2 cache, can it also be used for the P3 socket PGA370.
My nokia Ip530 has that type of CPU and as far as i know L2 cache is disabled
Regards, Marc
-----Original Message----- From: Keith Hui buurin@gmail.com To: coreboot@coreboot.org Cc: Jouni Mettälä jtmettala@gmail.com, Idwer Vollering vidwer@gmail.com, Roger rogerx.oss@gmail.com Subject: Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this Date: Tue, 11 Jan 2011 23:17:17 -0500
Hi all,
Here is the new L2 cache patch. Sign-off in the patch itself. Still very juicy and tasty at 25k. :D
Also done is including cpu/intel/model_68x again in slot_1. Otherwise it will die with a Coppermine P3 installed.
My boot log on P2B-LS and a Katmai 600MHz attached.
I have optimized it some more, and added more information and meaningful constants as I cross checked the code with Intel's documentation. Some debugging messages are different too. Give this a good workout.
Cheers Keith
ps. Copying people who have sent me reports. :)
On Fri, Jan 7, 2011 at 3:45 PM, Jouni Mettälä jtmettala@gmail.com wrote:
Hi Parts of original patch are already in coreboot. This version made cache work in my board now. It might need work so it doesn't break others. Here is part of serial capture. Rest is attached Initializing CPU #0 CPU: vendor Intel device 673 CPU: family 06, model 07, stepping 03 microcode_info: sig = 0x00000673 pf=0x00000001 rev = 0x00000000 microcode updated to revision: 0000000e from revision 00000000 Configuring L2 cache... rdmsr(IA32_PLATFORM_ID) = 0, 11020000 L2 Cache latency is 8 Sending 0 to set_l2_register4 L2 ECC Checking is enabled L2 Physical Address Range is 4096M Maximum cache mask is 20000 L2 Cache Mask is 4000 read_l2(2) = 8 write_l2(2) = 8 L2 Cache size is 512K L2 Cache lines initialized Signed-off-by: Jouni Mettälä jtmettala@gmail.com