Re: [LinuxBIOS] MB1030 / 3036 VGA resume

[Peter Stuge]

On Mon, May 08, 2006 at 07:27:07PM +0200, Christian Sühs wrote:
> Can somebody have a look to the gx1 datasheet on page 42 - 50.
>
> I'm not sure, but CR0 (Control Register 0) is set to 60000010h
> after a hardware reset.
> That means, that the 16K L1 Cache is disabled !?

Yep.
> I can't see any code in LB which enables L1 cache on cpu init.
>
> Could somebody compare this.

Hmm.

--8<-- include/cpu/x86/cache.h
static inline void enable_cache(void)
{
        unsigned long cr0;
        cr0 = read_cr0();
        cr0 &= 0x9fffffff;
        write_cr0(cr0);
}
-->8--

--8<-- cpu/x86/cache/cache.c
void x86_enable_cache(void)
{
        post_code(0x60);
        printk_info("Enabling cache\n");
        enable_cache();
}
-->8--

--8<-- cpu/amd/model_gx1/model_gx1_init.c
static void model_gx1_init(device_t dev)
{
#if 0
        gx1_cpu_setup();
        gx1_gx_setup();
#endif
        /* Turn on caching if we haven't already */
        x86_enable_cache();

/* Enable the local cpu apics */
        setup_lapic();
};

..

static struct device_operations cpu_dev_ops = {
        .init   = model_gx1_init,
};

-->8--

--8<-- cpu/amd/model_gx1/Config.lb
dir /cpu/x86/cache
driver model_gx1_init.o
-->8--

--8<-- Message-ID:  (Dec 2005)
Initializing CPU #0   
CPU: vendor Centaur device 698
Enabling cache
-->8--

That email is the only one I found from you to the list where
Enabling cache occurs. Check your serial output to see if it's still
there, as it should be.

//Peter