[coreboot] [PATCH 07/16] Port persimmon r6584 and r6601 to e350m1: SPI prefetch early

From: Scott Duplichan

Enable SPI cacheline prefetch early to reduce boot time.

Signed-off-by: Marshall Buschman 
---
 src/mainboard/asrock/e350m1/romstage.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 7f0b9df..41f9a6b 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -50,6 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
   // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
   __writemsr (0xc0010062, 0);

+  // early enable of PrefetchEnSPIFromHost
+  if (boot_cpu())
+    {
+    __outdword (0xcf8, 0x8000a3b8);
+    __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
+    }
+
   // early enable of SPI 33 MHz fast mode read
   if (boot_cpu())
     {