Author: uwe Date: 2007-11-13 17:24:15 +0100 (Tue, 13 Nov 2007) New Revision: 2966
Modified: trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/Options.lb trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/mainboard.c trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb Log: Random minor cosmetical or coding style fixes (trivial).
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/Options.lb 2007-11-13 15:40:21 UTC (rev 2965) +++ trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/Options.lb 2007-11-13 16:24:15 UTC (rev 2966) @@ -104,7 +104,6 @@ ## default HAVE_PIRQ_TABLE=1 default IRQ_SLOT_COUNT=5 -#object irq_tables.o
## ## Build code to export a CMOS option table
Modified: trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c 2007-11-13 15:40:21 UTC (rev 2965) +++ trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c 2007-11-13 16:24:15 UTC (rev 2966) @@ -38,7 +38,7 @@ #define POST_CODE(x) outb(x, 0x80) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-/* The alix1c has no SMBUS; the setup is hard-wired. */ +/* The ALIX1.C has no SMBus; the setup is hard-wired. */ void cs5536_enable_smbus(void) { } @@ -46,7 +46,8 @@ #include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-/* the part is a hynix hy5du121622ctp-d43 +/* The part is a Hynix hy5du121622ctp-d43. + * * HY 5D U 12 16 2 2 C <blank> T <blank> P D43 * Hynix * DDR SDRAM (5D) @@ -62,18 +63,17 @@ * Lead Free (P) * DDR400 3-3-3 (D43) */ -/* spd array */ -static u8 spdbytes[] = { +/* SPD array */ +static const u8 spdbytes[] = { [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10, [SPD_BANK_DENSITY] = 0x40, [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff, [SPD_MEMORY_TYPE] = 7, - [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* This is a guess for tRAC value */ - [SPD_MODULE_ATTRIBUTES] = 0xff, /* fix me later when we figure out */ + [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */ + [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */ [SPD_NUM_BANKS_PER_SDRAM] = 4, [SPD_PRIMARY_SDRAM_WIDTH] = 8, - /* alix1c is 1 bank. */ - [SPD_NUM_DIMM_BANKS] = 1, + [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */ [SPD_NUM_COLUMNS] = 0xa, [SPD_NUM_ROWS] = 3, [SPD_REFRESH] = 0x3a, @@ -91,7 +91,7 @@ print_debug("spd_read_byte dev "); print_debug_hex8(device);
- if (device != (0x50<<1)){ + if (device != (0x50 << 1)) { print_debug(" returns 0xff\n"); return 0xff; } @@ -101,14 +101,17 @@ print_debug(" returns "); print_debug_hex8(spdbytes[address]); print_debug("\r\n"); + return spdbytes[address]; }
-#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ -#define PLLMSRlo 0x02000030 -#define DIMM0 0xA0 -#define DIMM1 0xA2 +#define ManualConf 0 /* Do automatic strapped PLL config */ +#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ +#define PLLMSRlo 0x02000030 + +#define DIMM0 0xa0 +#define DIMM1 0xa2 + #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -119,9 +122,10 @@ static void msr_init(void) { msr_t msr; + /* Setup access to the MC for under 1MB. Note MC not setup yet. */ msr.hi = 0x24fffc02; - msr.lo = 0x10010000; + msr.lo = 0x10010000; wrmsr(CPU_RCONF_DEFAULT, msr);
msr.hi = 0x20000000; @@ -129,14 +133,13 @@ wrmsr(MSR_GLIU0 + 0x20, msr);
msr.hi = 0x20000000; - msr.lo = 0xfff00; + msr.lo = 0xfff00; wrmsr(MSR_GLIU1 + 0x20, msr); - }
+/** Early mainboard specific GPIO setup. */ static void mb_gpio_init(void) { - /* Early mainboard specific GPIO setup */ }
void cache_as_ram_main(void) @@ -144,7 +147,9 @@ static const struct mem_controller memctrl[] = { {.channel0 = {0x50}}, }; + extern void RestartCAR(); + POST_CODE(0x01);
SystemPreInit(); @@ -152,9 +157,8 @@
cs5536_early_setup();
- /* NOTE: must do this AFTER the early_setup! - * it is counting on some early MSR setup - * for cs5536 + /* NOTE: Must do this AFTER cs5536_early_setup()! + * It is counting on some early MSR setup for the CS5536. */ cs5536_disable_internal_uart(); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); @@ -169,17 +173,18 @@ sdram_initialize(1, memctrl);
/* Check memory */ - /* enable this only if you are having questions */ - /* ram_check(0x00000000, 640 * 1024);*/ + /* Enable this only if you are having questions. */ + /* ram_check(0, 640 * 1024); */
- /* Switch from Cache as RAM to real RAM - * There are two ways we could think about this. + /* Switch from Cache as RAM to real RAM. * + * There are two ways we could think about this. + * * 1. If we are using the auto.inc ROMCC way, the stack is * going to be re-setup in the code following this code. Just * wbinvd the stack to clear the cache tags. We don't care * where the stack used to be. - * + * * 2. This file is built as a normal .c -> .o and linked in * etc. The stack might be used to return etc. That means we * care about what is in the stack. If we are smart we set @@ -190,16 +195,16 @@ * located somewhere other than where LB would like it, you * need to write some code to do a copy from cache to RAM * - * We use method 1 on Norwich and on this board too. + * We use method 1 on Norwich and on this board too. */ POST_CODE(0x02); print_err("POST 02\n"); __asm__("wbinvd\n"); print_err("Past wbinvd\n"); - /* we are finding the return does not work on this - * board. Explicitly call the label that is after the call to - * us. This is gross, but sometimes at this level it is the - * only way out + + /* We are finding the return does not work on this board. Explicitly + * call the label that is after the call to us. This is gross, but + * sometimes at this level it is the only way out. */ done_cache_as_ram_main(); }
Modified: trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/irq_tables.c 2007-11-13 15:40:21 UTC (rev 2965) +++ trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/irq_tables.c 2007-11-13 16:24:15 UTC (rev 2966) @@ -20,7 +20,6 @@ #include <arch/pirq_routing.h> #include <console/console.h> #include <arch/io.h> -#include <arch/pirq_routing.h> #include "../../../southbridge/amd/cs5536/cs5536.h"
/* Platform IRQs */ @@ -41,7 +40,11 @@ #define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ #define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
-/* ALIX 1c interrupt wiring. Devices are: +/* + * ALIX1.C interrupt wiring. + * + * Devices are: + * * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31) * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block * 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) @@ -51,8 +54,11 @@ * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01) * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) + * * The only devices that interrupt are: - * What device IRQ PIN PIN WIRED TO + * + * What Device IRQ PIN PIN WIRED TO + * ------------------------------------------------- * AES 00:01.2 0a 01 A A * 3VPCI 00:0c.0 0a 01 A A * eth0 00:0d.0 0b 01 A B @@ -61,39 +67,40 @@ * usb 00:0f.4 0b 04 D D * usb 00:0f.5 0b 04 D D * - * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B -*/ + * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B. + */ + const struct irq_routing_table intel_irq_routing_table = { -PIRQ_SIGNATURE, /* u32 signature */ -PIRQ_VERSION, /* u16 version */ -32 + 16 * IRQ_SLOT_COUNT, -0x00, /* Where the interrupt router lies (bus) */ -(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ -0x00, /* IRQs devoted exclusively to PCI usage */ -0x100B, /* Vendor */ -0x002B, /* Device */ -0, /* Crap (miniport) */ -{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ -0x00, /* u8 checksum , this has to set to - * some value that would give 0 - * after the sum of all bytes - * for this structure - * (including checksum) - */ -{ - /* If you change the number of entries, - * change the IRQ_SLOT_COUNT above! - */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ - /* PCI SLOT */ - {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot1 */ - /* ONBOARD ETHER */ - {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ - /* MINI PCI */ - {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* mini slot2 */ - /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D */ - {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* Checksum */ + { + /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* PCI (slot 1) */ + {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, + + /* On-board ethernet */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* Mini PCI (slot 2) */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, + + /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, } };
Modified: trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/mainboard.c 2007-11-13 15:40:21 UTC (rev 2965) +++ trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/mainboard.c 2007-11-13 16:24:15 UTC (rev 2966) @@ -21,14 +21,13 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <arch/io.h> #include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> #include "../../../southbridge/amd/cs5536/cs5536.h" #include "chip.h"
-/* Print the platform configuration */ +/* Print the platform configuration. */ void print_conf(void) { #if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR int i; @@ -156,8 +155,8 @@
static void init(struct device *dev) { - printk_debug("ALIX1C ENTER %s\n", __FUNCTION__); - printk_debug("ALIX1C EXIT %s\n", __FUNCTION__); + printk_debug("ALIX1.C ENTER %s\n", __FUNCTION__); + printk_debug("ALIX1.C EXIT %s\n", __FUNCTION__); }
static void enable_dev(struct device *dev)
Modified: trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb 2007-11-13 15:40:21 UTC (rev 2965) +++ trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb 2007-11-13 16:24:15 UTC (rev 2966) @@ -4,22 +4,21 @@ option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use -## (normal AND fallback images and payloads). -## leave 36k for vsa -## -option ROM_SIZE = 512*1024 - 36 * 1024 +## (normal AND fallback images and payloads). Leave 36k for VSA. +option ROM_SIZE = (512 * 1024) - (36 * 1024)
## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image, ## not including any payload. -option ROM_IMAGE_SIZE=64*1024 +option ROM_IMAGE_SIZE = (64 * 1024)
option FALLBACK_SIZE = ROM_SIZE
option DEFAULT_CONSOLE_LOGLEVEL = 3 option MAXIMUM_CONSOLE_LOGLEVEL = 11 -romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option LINUXBIOS_EXTRA_VERSION=".0Fallback" + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option LINUXBIOS_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end