Rudolf Marek wrote:
- /* ROM memory cycles go to LPC. */
- /* Only ROM memory cycles go to LPC. */
I think it should be,
- /* Only memory ROM cycles go to LPC. */
Because this bit is telling if all memory cycles should go to LPC or just those from ROM range. Please try to rephase that.
Updated patch:
Comment changes, add pointer to PCIe bridge documentation.
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/southbridge/via/k8t890/k8t890_ctrl.c =================================================================== --- src/southbridge/via/k8t890/k8t890_ctrl.c.orig 2010-11-03 14:53:07.000000000 +0100 +++ src/southbridge/via/k8t890/k8t890_ctrl.c 2010-11-03 15:51:23.000000000 +0100 @@ -154,7 +154,11 @@
pci_write_config8(dev, 0x47, 0x30);
- /* VT8237R specific configuration other SB are done in their own directories */ + /* + * VT8237R specific configuration, + * other SB are done in their own directories: + * VT8237A and VT8237S are handled in vt8237_ctrl.c + */
device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); Index: src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- src/southbridge/via/vt8237r/vt8237r_lpc.c.orig 2010-11-03 15:50:51.000000000 +0100 +++ src/southbridge/via/vt8237r/vt8237r_lpc.c 2010-11-03 16:02:37.000000000 +0100 @@ -457,7 +457,18 @@ /* I/O recovery time, default IDE routing */ pci_write_config8(dev, 0x4c, 0x04);
- /* ROM memory cycles go to LPC. */ + /* + * Bit | Meaning + * 7 | 1: Only ROM memory cycles go to LPC instead of all memory + * | cycles. + * 6 | 0: Internal ISA cycles do not arbitrate with secondary IDE + * 5 | 0: Disable LPC RTC + * 4 | 0: Disable LPC Keyboard + * 3 | 0: Disable Port 0x62/0x66 to LPC + * 2 | 0: Disable Port 0x62/0x66 MCCS# chipselect decoding + * 1 | 0: Disable A20M# signal (signal not asserted) + * 0 | 0: Disable NMI on PCI parity error + */ pci_write_config8(dev, 0x59, 0x80);
/* @@ -479,7 +490,18 @@ /* I/O recovery time, default IDE routing */ pci_write_config8(dev, 0x4c, 0x44);
- /* ROM memory cycles go to LPC. */ + /* + * Bit | Meaning + * 7 | 1: Only ROM memory cycles go to LPC instead of all memory + * | cycles. + * 6 | 0: Internal ISA cycles do not arbitrate with secondary IDE + * 5 | 0: Disable LPC RTC + * 4 | 0: Disable LPC Keyboard + * 3 | 0: Disable Port 0x62/0x66 to LPC + * 2 | 0: Disable Port 0x62/0x66 MCCS# chipselect decoding + * 1 | 0: Disable A20M# signal (signal not asserted) + * 0 | 0: Disable NMI on PCI parity error + */ pci_write_config8(dev, 0x59, 0x80);
/* Index: src/southbridge/via/k8t890/k8t890_pcie.c =================================================================== --- src/southbridge/via/k8t890/k8t890_pcie.c.orig 2010-11-03 14:53:07.000000000 +0100 +++ src/southbridge/via/k8t890/k8t890_pcie.c 2010-11-03 15:51:23.000000000 +0100 @@ -24,6 +24,12 @@ #include <device/pci_ids.h> #include "k8t890.h"
+/* + * Note: + * The pcie bridges are similar to the VX800 ones documented at + * http://linux.via.com.tw/ + */ + static void peg_init(struct device *dev) { u8 reg;