[coreboot] [Fwd: Re: Via VT82C686 (A/B) southbridge]

[a a]

i have a board working with this chip and i have the docs
it's a quite old tree and i needed some patches to get it working i will
put it online as soon as i find the backup
afaik the docs are public ...

Reinder
> On Sat, Mar 22, 2008 at 11:43 PM, Jacek Chruscik  > wrote:
> Hi,
>
> Does anybody know how to deal with this southbridge: VIA VT82c686
> I'm trying to port coreboot v.2 for FIC FR33E motherboard, but this
> southbridge has the superio built in.
> I don't have any datasheet for this chip.
> coreboot-v2 has no option for such superio, and all I need to do is to
> initialize serial port.
> As a base I used via-epia code. The north is vt8601.
>
> So far I generated PIRQ table, modified auto.c to recognize correct
> southbridge, modified config.lb  to initialize
> devices.
>
> There is serial init function in vt82c686 source:
>
> static void vt82c686_enable_serial(device_t dev, unsigned iobase)
> .....
>
> but it requires 2 parameters, which I don't have (called as early
> serial init from auto.c):
>
>
> dev is the ISA/LPC device in the southbridge, with device ID 0x0686. 
> iobase is the serial io base, usually 0x3f8 for the first port, and 
> 0x2f8 for the second one (although I doubt the second one will work, 
> without some modification).
>
> -Corey

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