[coreboot] Reviewers for src/soc/intel/

[Compostella, Jeremy]

Hi,

I do not know who I should talk to so I am going to leverage the mailing list.

I have been wondering: why have I not been looped in the review [85827 soc/intel/pantherlake: Refactor FSP-M params for debug message control].

I looked at the `MAINTAINERS' file and I found the following related definitions.

,----
| INTEL SUPPORT
| R:      Intel_Coreboot_Reviewers 
| S:      Maintained
| F:      src/vendorcode/intel/
| F:      src/cpu/intel/
| F:      src/northbridge/intel/
| F:      src/southbridge/intel/
| F:      src/soc/intel/
| F:      src/drivers/intel/
| F:      src/include/cpu/intel/
| [...]
| INTEL PANTHERLAKE SOC
| M:      Subrata Banik 
| M:      Kapil Porwal 
| M:      Pranava Y N 
| S:      Maintained
| F:      src/soc/intel/pantherlake/
`----

I am part of the Intel_Coreboot_Reviewers  mailing list but I do not see *Intel_Coreboot_Reviewers* added to the CC section in gerrit which probably explain why I did not get any email.

Our goal is to have Intel folks of this mailing list as reviewers of all the src/soc/intel/... changes. How can we achieve that ?

Regards,